Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 796

19.1.57 CES — Correctable Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 110h
Default Value:
Bit
31:14 Reserved
Advisory Non-Fatal Error Status (ANFES) — R/WC.
13
0 = Advisory Non-Fatal Error did not occur.
1 = Advisory Non-Fatal Error did occur.
12 Replay Timer Timeout Status (RTT) — R/WC. Indicates the replay timer timed out.
11:9 Reserved
Replay Number Rollover Status (RNR) — R/WC. Indicates the replay number rolled
8
over.
7 Bad DLLP Status (BD) — R/WC. Indicates a bad DLLP was received.
6 Bad TLP Status (BT) — R/WC. Indicates a bad TLP was received.
5:1 Reserved
0 Receiver Error Status (RE) — R/WC. Indicates a receiver error occurred.
19.1.58 CEM — Correctable Error Mask Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 114h
Default Value:
When set, the corresponding error in the CES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
Bit
31:14 Reserved
Advisory Non-Fatal Error Mask (ANFEM) — R/WO.
0 = Does not mask Advisory Non-Fatal errors.
1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control
13
This register is set by default to enable compatibility with software that does not
comprehend Role-Based Error Reporting.
NOTE: The correctable error detected bit in device status register is set whenever the
12 Replay Timer Timeout Mask (RTT) — R/WO. Mask for replay timer timeout.
11:9 Reserved
8 Replay Number Rollover Mask (RNR) — R/WO. Mask for replay number rollover.
7 Bad DLLP Mask (BD) — R/WO. Mask for bad DLLP reception.
6 Bad TLP Mask (BT) — R/WO. Mask for bad TLP reception.
5:1 Reserved
0 Receiver Error Mask (RE) — R/WO. Mask for receiver errors.
796
113h
–
00000000h
117h
–
00002000h
register and (b) updating the Uncorrectable Error Status register.
Advisory Non-Fatal error is detected, independent of this mask bit.
PCI Express* Configuration Registers
Attribute: R/WC
Size: 32 bits
Description
Attribute: R/WO
Size: 32 bits
Description
Datasheet