Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 872

23.1.11 CAPP—Capabilities List Pointer Register
(MEI—D22:F0)
Address Offset: 34h
Default Value:
Bit
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
7:0
capabilities list is at 50h in configuration space.
23.1.12 INTR—Interrupt Information Register
(MEI—D22:F0)
Address Offset: 3Ch–3Dh
Default Value:
Bit
Interrupt Pin (IPIN) — RO. This indicates the interrupt pin the Intel MEI host
15:8 controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy
interrupt on INTA/INTB/INTC/INTD, respectively.
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line
7:0
(vector) the interrupt is connected to. No hardware action is taken on this register.
23.1.13 HFS—Host Firmware Status Register
(MEI—D22:F0)
Address Offset: 40h–43h
Default Value:
Bit
Host Firmware Status (HFS) — RO. This register field is used by Firmware to reflect
31:0
the operating environment to the host.
872
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
50h
0400h
00000000h
Attribute: RO
Size: 8 bits
Description
Attribute: R/W, RO
Size: 16 bits
Description
Attribute: RO
Size: 32 bits
Description
Datasheet