Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 931

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.10.4 KTIER—KT Interrupt Enable Register (KT—D23:F3)
Address Offset: 01h
Default Value:
This implements the KT Interrupt Enable register. Host access to this address, depends
on the state of the DLAB bit (KTLCR[7]). It must be "0" to access this register. The bits
enable specific events to interrupt the Host.
Bit
7:4
3
2
1
0
23.10.5 KTDLMR—KT Divisor Latch MSB Register (KT—D23:F3)
Address Offset: 01h
Default Value:
Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this
bit is 0, Host accesses the KTIER.
This is the standard Serial interface's Divisor Latch register's MSB. This register is only
for SW compatibility and does not affect performance of the hardware.
Bit
7:0
Datasheet
00h
Reserved
MSR (IER2)— R/W. When set, this bit enables bits in the Modem Status register to
cause an interrupt to the host.
LSR (IER1)— R/W.When set, this bit enables bits in the Receiver Line Status
Register to cause an Interrupt to the Host.
THR (IER1)— R/W. When set, this bit enables an interrupt to be sent to the Host
when the transmit Holding register is empty.
DR (IER0)— R/W. When set, the Received Data Ready (or Receive FIFO Timeout)
interrupts are enabled to be sent to Host.
00h
Divisor Latch MSB (DLM)— R/W. Implements the Divisor Latch MSB register of the
Serial Interface.
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
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