Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 592

14.4.1.2 GHC—Global PCH Control Register (D31:F2)
Address Offset: ABAR + 04h–07h
Default Value:
Bit
AHCI Enable (AE) — R/W. When set, this bit indicates that an AHCI driver is loaded
and the controller will be talked to using AHCI mechanisms. This can be used by an PCH
that supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the
controller will not be talked to as legacy.
31
0 = Software will communicate with the PCH using legacy mechanisms.
1 = Software will communicate with the PCH using AHCI. The PCH will not have to allow
Software shall set this bit to 1 before accessing other AHCI registers.
30:3 Reserved
MSI Revert to Single Message (MRSM) — RO: When set to 1 by hardware, this bit
indicates that the host controller requested more than one MSI vector but has reverted
to using the first vector only. When this bit is cleared to 0, the Controller has not
reverted to single MSI mode (that is, hardware is already in single MSI mode, software
has allocated the number of messages requested, or hardware is sharing interrupt
vectors if MC.MME < MC.MMC).
2
When this bit is set to 1, single MSI mode operation is in use and software is
responsible for clearing bits in the IS register to clear interrupts.
This bit shall be cleared to 0 by hardware when any of the four conditions stated is
false. This bit is also cleared to 0 when MC.MSIE = 1 and MC.MME = 0h. In this case,
the hardware has been programmed to use single MSI mode, and is not "reverting" to
that mode.
For PCH, the Controller shall always revert to single MSI mode when the number of
vectors allocated by the host is less than the number requested. This bit is ignored
when GHC.HR = 1.
Interrupt Enable (IE) — R/W. This global bit enables interrupts from the PCH.
1
0 = All interrupt sources from all ports are disabled.
1 = Interrupts are allowed from the AHCI controller.
Controller Reset (HR) — R/W. Resets the PCH AHCI controller.
0 = No effect
1 = When set by software, this bit causes an internal reset of the PCH AHCI controller.
0
NOTE: For further details, consult Section 10.4.3 of the Serial ATA Advanced Host
592
00000000h
command processing using both AHCI and legacy mechanisms.
"MC.MSIE = 1 (MSI is enabled)
"MC.MMC > 0 (multiple messages requested)
"MC.MME > 0 (more than one message allocated)
"MC.MME!= MC.MMC (messages allocated not equal to number requested)
All state machines that relate to data transfers and queuing return to an idle
condition, and all ports are re-initialized using COMRESET.
Controller Interface specification revision 1.3.
SATA Controller Registers (D31:F2)
Attribute: R/W, RO
Size: 32 bits
Description
Datasheet