Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 714

17.1.2.9 GSTS—Global Status Register
®
(Intel
Memory Address:HDBAR + 10h
Default Value:
Bit
15:2
1
0
17.1.2.10 OUTSTRMPAY—Output Stream Payload Capability
®
(Intel
Memory Address:HDBAR + 18h
Default Value:
Bit
15:8 Reserved
Output Stream Payload Capability (OUTSTRMPAY)— RO: Indicates maximum
number of words per frame for any single output stream. This measurement is in 16 bit
word quantities per 48 kHz frame. 48 Words (96B) is the maximum supported,
therefore a value of 30h is reported in this register. Software must ensure that a format
which would cause more words per frame than indicated is not programmed into the
7:0
Output Stream Descriptor register.
00h = 0 words
01h = 1 word payload
...
FFh = 255h word payload
17.1.2.11 INSTRMPAY—Input Stream Payload Capability
®
(Intel
Memory Address:HDBAR + 1Ah
Default Value:
Bit
15:8 Reserved
Input Stream Payload Capability (INSTRMPAY)— RO. Indicates maximum number
of words per frame for any single input stream. This measurement is in 16 bit word
quantities per 48 kHz frame. 24 Words (48B) is the maximum supported, therefore a
value of 18h is reported in this register. Software must ensure that a format which
would cause more words per frame than indicated is not programmed into the Input
7:0
Stream Descriptor register.
00h = 0 words
01h = 1 word payload
...
FFh = 255h word payload
714
High Definition Audio Controller—D27:F0)
0000h
Reserved.
Flush Status — R/WC. This bit is set to 1 by hardware to indicate that the flush cycle
initiated when the Flush Control bit (HDBAR + 08h, bit 1) was set has completed.
Software must write a 1 to clear this bit before the next time the Flush Control bit is
set to clear the bit.
Reserved.
High Definition Audio Controller—D27:F0)
0030h
High Definition Audio Controller—D27:F0)
0018h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
Description
Attribute:
Size:
Description
Attribute:
Size:
Description
R/WC
16 bits
RO
16 bits
RO
16 bits
Datasheet