Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 775

PCI Express* Configuration Registers
Bit
11:10
9:4
3:0
Datasheet
Active State Link PM Support (APMS) — R/WO. Indicates what level of active state
link power management is supported on the root port.
Bits Definition
00b Neither L0s nor L1 are supported
01b L0s Entry Supported
10b L1 Entry Supported
11b Both L0s and L1 Entry Supported
Maximum Link Width (MLW) — RO. For the root ports, several values can be taken,
based upon the value of the chipset config register field RPC.PC1 (Chipset Config
Registers:Offset 0224h:bits1:0) for Ports 1-4 and RPC.PC2 (Chipset Config
Registers:Offset 0224h:bits1:0) for Ports 5 and 6
Value of MLW Field
Port # RPC.PC1=00b
1 01h
2 01h
3 01h
4 01h
Port # RPC.PC2=00b
5 01h
6 01h
7 01h
8 01h
Maximum Link Speed (MLS) — RO.
0001b = indicates the link speed is 2.5 Gb/s
0010b = 5.0 Gb/s and 2.5Gb/s link speeds supported
These bits report a value of 0001b if Gen2 disable bit 14 is set in the MPC register, else
the value reported is 0010b
Description
RPC.PC1=11b
04h
01h
01h
01h
RPC.PC2=11b
04h
01h
01h
01h
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