Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 853

Thermal Sensor Registers (D31:F6)
22.1.23 PCS—Power Management Control And Status
Address Offset: 54h
Default Value:
Bit
31:24
23
22
21:16
15
14:9
8
7:4
3
2
1:0
Datasheet
57h
–
0008h
Data — RO. Does not apply. Hardwired to 0s.
Bus Power/Clock Control Enable (BPCCE) — RO. Hardwired to 0.
B2/B3 Support (B23) — RO. Does not apply. Hardwired to 0.
Reserved
PME Status (PMES) — RO. This bit is always 0, since this PCI Function does not
generate PME#.
Reserved
PME Enable (PMEE) — RO. This bit is always zero, since this PCI Function does not
generate PME#.
Reserved
No Soft Reset — RO. When set 1, this bit indicates that devices transitioning from
D3 to D0 because of PowerState commands do not perform an internal reset.
HOT
Configuration context is preserved. Upon transition from D3
no additional operating system intervention is required to preserve Configuration
Context beyond writing the PowerState bits.
Reserved
Power State (PS) — R/W. This field is used both to determine the current power
state of the Thermal controller and to set a new power state. The values are:
00 = D0 state
11 = D3 state
HOT
If software attempts to write a value of 10b or 01b in to this field, the write operation
must complete normally; however, the data is discarded and no state change occurs.
When in the D3 states, the Thermal controller's configuration space is available, but
HOT
the I/O and memory spaces are not. Additionally, interrupts are blocked.
When software changes this value from the D3
warm (soft) reset is generated.
Attribute: R/W, RO
Size: 32 bits
Description
HOT
state to the D0 state, no internal
HOT
to D0 initialized state,
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