Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 481

LPC Interface Bridge Registers (D31:F0)
13.2.11 DMA_WRMSK—DMA Write All Mask Register
I/O Address:
Default Value:
Lockable:
Bit
7:4
3:0
13.3 Timer I/O Registers
Port
40h
41h
42h
43h
Datasheet
Ch. #0 3 = 0Fh;
–
Ch. #4 7 = DEh
–
0000 1111
No
Reserved. Must be 0.
Channel Mask Bits — R/W. This register permits all four channels to be
simultaneously enabled/disabled instead of enabling/disabling each channel
individually, as is the case with the Mask Register – Write Single Mask Bit. In addition,
this register has a read path to allow the status of the channel mask bits to be read. A
channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register
reaches terminal count (unless the channel is in auto-initialization mode).
Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0
enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master
Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status.
Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked
Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked
Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked
Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked
NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channels
0–3 through channel 4.
Aliases
Counter 0 Interval Time Status Byte Format
50h
Counter 0 Counter Access Port
Counter 1 Interval Time Status Byte Format
51h
Counter 1 Counter Access Port
Counter 2 Interval Time Status Byte Format
52h
Counter 2 Counter Access Port
Timer Control Word
53h Timer Control Word Register
Counter Latch Command
Attribute:
Size:
Power Well:
Description
Register Name
R/W
8-bit
Core
Default Value Type
0XXXXXXXb RO
Undefined R/W
0XXXXXXXb RO
Undefined R/W
0XXXXXXXb RO
Undefined R/W
Undefined WO
XXXXXXX0b WO
X0h WO
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