Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 830

Bit
Upper Write Granularity (UWG) — R/W. This register is locked by the Vendor
Component Lock (UVCL) bit.
0 = 1 Byte
1 = 64 Byte
NOTES:
2
1.
2.
Upper Block/Sector Erase Size (UBES)— R/W. This field identifies the erasable
sector size for all Flash components.
Valid Bit Settings:
00 = 256 Byte
01 = 4 KB
10 = 8 KB
1:0
11 = 64 KB
This register is locked by the Vendor Component Lock (UVCL) bit.
Hardware takes no action based on the value of this register. The contents of this
register are to be used only by software and can be read in the HSFSTS.BERASE
register in both the BIOS and the GbE program registers if FLA is greater or equal to
FPBA.
21.1.29 FPB — Flash Partition Boundary
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: This register is only applicable when SPI device is in descriptor mode.
Bit
31:13 Reserved.
Flash Partition Boundary Address (FPBA) — RO. This register reflects the value of
12:0
Flash Descriptor Component FPBA field.
830
If more than one Flash component exists, this field must be set to the lowest
common write granularity of the different Flash components.
If using 64 B write, BIOS must ensure that multiple byte writes do not occur
over 256 B boundaries. This will lead to corruption as the write will wrap around
the page boundary on the SPI flash part. This is a a feature page writable SPI
flash.
SPIBAR + D0h
00000000h
Serial Peripheral Interface (SPI)
Description
Attribute: RO
Size: 32 bits
Description
Datasheet