Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 829

Serial Peripheral Interface (SPI)
21.1.28 UVSCC— Host Upper Vendor Specific Component
Capabilities Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: All attributes described in UVSCC must apply to all flash space equal to or above the
FPBA, even if it spans between two separate flash parts. This register is only applicable
when SPI device is in descriptor mode.
Note: To prevent this register from being modified you must use LVSCC.VCL bit.
Bit
31:16 Reserved.
Upper Erase Opcode (UEO)— R/W. This register is programmed with the Flash erase
instruction opcode required by the vendor's Flash component.
15:8
This register is locked by the Vendor Component Lock (UVCL) bit.
7:5 Reserved
Write Enable on Write Status (UWEWS) — R/W. This register is locked by the
Vendor Component Lock (UVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash's status register)
1 = A write of 00h to the SPI flash's status register will be sent on EVERY write and
4
NOTES:
1.
2.
3.
Upper Write Status Required (UWSR) — R/W. This register is locked by the Vendor
Component Lock (UVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash's status register)
1 = A write of 00h to the SPI flash's status register will be sent on EVERY write and
3
NOTES:
1.
2.
3.
Datasheet
SPIBAR + C8h
00000000h
erase to the SPI flash. 06h 01h 00h is the opcode sequence used to unlock the
Status register.
This bit should not be set to 1 if there are non volatile bits in the SPI flash's
status register. This may lead to premature flash wear out.
This is not an atomic sequence. If the SPI component's status register is non-
volatile, then BIOS should issue an atomic software sequence cycle to unlock
the flash part.
Bit 3 and bit 4 should NOT be both set to 1.
erase to the SPI flash. 50h 01h 00h is the opcode sequence used to unlock the
Status register.
This bit should not be set to '1' if there are non volatile bits in the SPI flash's
status register. This may lead to premature flash wear out.
This is not an atomic sequence. If the SPI component's status register is non-
volatile, then BIOS should issue an atomic software sequence cycle to unlock
the flash part.
Bit 3 and bit 4 should NOT be both set to 1.
Attribute: RO, R/WL
Size: 32 bits
Description
829