Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 409

Chipset Configuration Registers
10.1.79 MISCCTL—Miscellaneous Control Register
Offset Address: 3590–3594h
Default Value:
This register is in the suspend well. This register is not reset on D3-to-D0, HCRESET
nor core well reset.
Bit
31:2
1
0
Datasheet
00000000h
Reserved.
EHCI 2 USBR Enable — R/W. When set, this bit enables support for the USB-r
redirect device on the EHCI controller in Device 26. SW must complete programming
the following registers before this bit is set:
1. Enable RMH
2. HCSPARAMS (N_CC, N_Ports)
EHCI 1 USBR Enable — R/W. When set, this bit enables support for the USB-r
redirect device on the EHCI controller in Device 29. SW must complete programming
the following registers before this bit is set:
1. Enable RMH
2. HCSPARAMS (N_CC, N_Ports)
Attribute: R/W
Size: 32-bit
Description
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