Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 919

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.8.9 IDESBMCR—IDE Secondary Bus Master Command
Register (IDER—D22:F2)
Address Offset: 08h
Default Value:
Bit
7:4
3
2:1
0
23.8.10 IDESBMDS0R—IDE Secondary Bus Master Device
Specific 0 Register (IDER—D22:F2)
Address Offset: 09h
Default Value:
Bit
7:0
23.8.11 IDESBMSR—IDE Secondary Bus Master Status
Register (IDER—D22:F2)
Address Offset: 0Ah
Default Value:
Bit
7
6
5
4:0
Datasheet
00h
Reserved
Read Write Command (RWC) — R/W. This bit sets the direction of bus master
transfer. When 0, Reads are performed from system memory; when 1, writes are
performed to System Memory. This bit should not be changed when the bus master
function is active.
Reserved
Start/Stop Bus Master (SSBM) — R/W. This bit gates the bus master operation of
IDE function when zero.
Writing 1 enables the bus master operation. Bus master operation can be halted by
writing a 0 to this bit. Operation cannot be stopped and resumed.
This bit is cleared after data transfer is complete as indicated by either the BMIA bit
or the INT bit of the Bus Master status register is set or both are set.
00h
Device Specific Data0 (DSD0) — R/W. This register implements the bus master
Device Specific 1 register of the secondary channel. This register is programmed by
the Host.
80h
Simplex Only (SO) — R/W. This bit indicates whether both Bus Master Channels can
be operated at the same time or not.
0 = Both can be operated independently
1 = Only one can be operated at a time.
Drive 1 DMA Capable (D1DC) — R/W. This bit is read/write by the host.
Drive 0 DMA Capable (D0DC) — R/W. This bit is read/write by the host.
Reserved
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W, RO
Size: 8 bits
Description
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