Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 725

®
Integrated Intel High Definition Audio Controller Registers
17.1.2.35 SDCTL—Stream Descriptor Control Register
®
(Intel
Memory Address:Input Stream[0]: HDBAR + 80h
Default Value:
Bit
Stream Number — R/W. This value reflect the Tag associated with the data being
transferred on the link.
When data controlled by this descriptor is sent out over the link, it will have its stream
number encoded on the SYNC signal.
When an input stream is detected on any of the SDI signals that match this value, the
data samples are loaded into FIFO associated with this descriptor.
Note that while a single SDI input may contain data from more than one stream
23:20
number, two different SDI inputs may not be configured with the same stream number.
0000 = Reserved
0001 = Stream 1
........
1110 = Stream 14
1111 = Stream 15
Bidirectional Direction Control — RO. This bit is only meaningful for bidirectional
19
streams; therefore, this bit is hardwired to 0.
Traffic Priority — RO. Hardwired to 1 indicating that all streams will use VC1 if it is
18
enabled through the PCI Express* registers.
Stripe Control — RO. This bit is only meaningful for input streams; therefore, this bit is
17:16
hardwired to 0.
15:5 Reserved
Descriptor Error Interrupt Enable — R/W.
4 0 = Disable
1 = An interrupt is generated when the Descriptor Error Status bit is set.
FIFO Error Interrupt Enable — R/W.
This bit controls whether the occurrence of a FIFO error (overrun for input or underrun
3
for output) will cause an interrupt or not. If this bit is not set, bit 3in the Status register
will be set, but the interrupt will not occur. Either way, the samples will be dropped.
Interrupt on Completion Enable — R/W.
This bit controls whether or not an interrupt occurs when a buffer completes with the
2
IOC bit set in its descriptor. If this bit is not set, bit 2 in the Status register will be set,
but the interrupt will not occur.
Datasheet
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + A0h
Input Stream[2]: HDBAR + C0h
Input Stream[3]: HDBAR + E0h
Output Stream[0]: HDBAR + 100h
Output Stream[1]: HDBAR + 120h
Output Stream[2]: HDBAR + 140h
Output Stream[3]: HDBAR + 160h
040000h
Attribute:
Size:
Description
R/W, RO
24 bits
725