Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 917

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.8.3 IDEPBMSR—IDE Primary Bus Master Status
Register (IDER—D22:F2)
Address Offset: 02h
Default Value:
Bit
7
6
5
4:3
2
1
0
23.8.4 IDEPBMDS1R—IDE Primary Bus Master Device
Specific 1 Register (IDER—D22:F2)
Address Offset: 03h
Default Value:
Bit
7:0
23.8.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor
Table Pointer Byte 0 Register (IDER—D22:F2)
Address Offset: 04h
Default Value:
Bit
7:0
Datasheet
80h
Simplex Only (SO) — RO. Value indicates whether both Bus Master Channels can be
operated at the same time or not.
0 = Both can be operated independently
1 = Only one can be operated at a time.
Drive 1 DMA Capable (D1DC) — R/W. This bit is read/write by the host (not write 1
clear).
Drive 0 DMA Capable (D0DC) — R/W. This bit is read/write by the host (not write 1
clear).
Reserved
Interrupt (INT) — R/W. This bit is set by the hardware when it detects a positive
transition in the interrupt logic (refer to IDE host interrupt generation diagram).The
hardware will clear this bit when the Host SW writes 1 to it.
Error (ER) — R/W. Bit is typically set by FW. Hardware will clear this bit when the
Host SW writes 1 to it.
Bus Master IDE Active (BMIA) — RO. This bit is set by hardware when SSBM
register is set to 1 by the Host. When the bus master operation ends (for the whole
command) this bit is cleared by FW. This bit is not cleared when the HOST writes 1 to
it.
00h
Device Specific Data1 (DSD1) — R/W. Device Specific Data.
00h
Descriptor Table Pointer Byte 0 (DTPB0) — R/W. This register implements the
Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the primary channel. This register is read/write by the HOST
interface.
Attribute: RO, R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
917