Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 724

17.1.2.33 DPLBASE—DMA Position Lower Base Address Register
®
(Intel
Memory Address:HDBAR + 70h
Default Value:
Bit
DMA Position Lower Base Address — R/W. Lower 32 bits of the DMA Position Buffer
Base Address. This register field must not be written when any DMA engine is running
31:7 or the DMA transfer may be corrupted. This same address is used by the Flush Control
and must be programmed with a valid value before the Flush Control bit
(HDBAR+08h:bit 1) is set.
DMA Position Lower Base Unimplemented bits — RO. Hardwired to 0 to force the 128-
6:1
byte buffer alignment for cache line write optimizations.
DMA Position Buffer Enable — R/W.
1 = Controller will write the DMA positions of each of the DMA engines to the buffer in
0
17.1.2.34 DPUBASE—DMA Position Upper Base Address Register
®
(Intel
Memory Address:HDBAR + 74h
Default Value:
Bit
DMA Position Upper Base Address — R/W. Upper 32 bits of the DMA Position Buffer
31:0 Base Address. This register field must not be written when any DMA engine is running
or the DMA transfer may be corrupted.
724
High Definition Audio Controller—D27:F0)
00000000h
the main memory periodically (typically once per frame). Software can use this
value to know what data in memory is valid data.
High Definition Audio Controller—D27:F0)
00000000h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
Description
Attribute:
Size:
Description
R/W, RO
32 bits
R/W
32 bits
Datasheet