Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 925

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.9.7 CLS—Cache Line Size Register (KT—D22:F3)
Address Offset: 0Ch
Default Value:
This register defines the system cache line size in DWORD increments. Mandatory for
master which use the Memory-Write and Invalidate command.
Bit
7:0
23.9.8 KTIBA—KT IO Block Base Address Register
(KT—D22:F3)
Address Offset: 10–13h
Default Value:
Bit
31:16
15:3
2:1
0
23.9.9 KTMBA—KT Memory Block Base Address Register
(KT—D22:F3)
Address Offset: 14–17h
Default Value:
Bit
31:12
11:4
3
2:1
0
Datasheet
00h
Cache Line Size (CLS)— RO. All writes to system memory are Memory Writes.
00000001h
Reserved
Base Address (BAR)— R/W. This field provides the base address of the I/O space (8
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE)— RO. This bit indicates a request for I/O space
00000000h
Base Address (BAR)— R/W. This field provides the base address for Memory
Mapped I,O BAR. Bits 31:12 correspond to address signals 31:12.
Reserved
Prefetchable (PF)— RO. This bit indicates that this range is not pre-fetchable.
Type (TP)— RO. This field indicates that this range can be mapped anywhere in 32-
bit address space.
Resource Type Indicator (RTE)— RO. This bit indicates a request for register
memory space.
Attribute: RO
Size: 8 bits
Description
Attribute: RO, R/W
Size: 32 bits
Description
Attribute: RO, R/W
Size: 32 bits
Description
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