Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 631

SATA Controller Registers (D31:F5)
15.1.30 FLRCLV— FLR Capability Length and Value (SATA–D31:F5)
Address Offset: B2h–B3h
Default Value:
Function Level Reset:No (Bits 9:8 only)
When FLRCSSEL = 0, this register is defined as follows:
Bit
15:10 Reserved.
9 FLR Capability — R/WO. This field indicates support for Function Level Reset.
TXP Capability — R/WO. This field indicates support for the Transactions Pending
8
(TXP) bit. TXP must be supported if FLR is supported.
Capability Length — RO. This field indicates the number of bytes of the Vendor
7:0 Specific capability as required by the PCI specification. It has the value of 06h for FLR
Capability.
When FLRCSSEL = 1, this register is defined as follows:
Bit
Vendor Specific Capability ID — RO. A value of 02h identifies this capability as a
15:12
Function Level Reset.
11:8 Capability Version — RO. This field indicates the version of the FLR capability.
Capability Length — RO. This field indicates the number of bytes of the Vendor
7:0 Specific capability as required by the PCI specification. It has the value of 06h for FLR
Capability.
15.1.31 FLRCTRL— FLR Control (SATA–D31:F5)
Address Offset: B4h–B5h
Default Value:
Bit
15:9 Reserved.
Transactions Pending (TXP) — RO.
8
0 = Completions for all Non-Posted requests have been received by the controller.
1 = Controller has issued Non-Posted request which has not been completed.
7:1 Reserved.
Initiate FLR — R/W. Used to initiate FLR transition. A write of 1 indicates FLR
0
transition.
Datasheet
2006h
0000h
Attribute: RO, R/WO
Size: 16 bits
Description
Description
Attribute: R/W, RO
Size: 16 bits
Description
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