Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 742

18.1.6 PI—Programming Interface Register (SMBus—D31:F3)
Offset Address: 09h
Default Value:
Bit
7:0 Reserved
18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)
Address Offset: 0Ah
Default Value:
Bit
Sub Class Code (SCC) — RO.
7:0
05h = SMBus serial controller
18.1.8 BCC—Base Class Code Register (SMBus—D31:F3)
Address Offset: 0Bh
Default Value:
Bit
Base Class Code (BCC) — RO.
7:0
0Ch = Serial controller.
18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0
(SMBus—D31:F3)
Address Offset: 10–13h
Default Value:
Bit
Base Address — R/W. Provides the 32 byte system memory base address for the PCH
31:8
SMB logic.
7:4 Reserved
Prefetchable (PREF) — RO. Hardwired to 0. Indicates that SMBMBAR is not pre-
3
fetchable.
Address Range (ADDRNG) — RO. Indicates that this SMBMBAR can be located
2:1
anywhere in 64 bit address space. Hardwired to 10b.
Memory Space Indicator — RO. This read-only bit always is 0, indicating that the
0
SMB logic is Memory mapped.
742
00h
05h
0Ch
00000004h
SMBus Controller Registers (D31:F3)
Attribute: RO
Size: 8 bits
Description
Attributes: RO
Size: 8 bits
Description
Attributes: RO
Size: 8 bits
Description
Attributes: R/W, RO
Size: 32 bits
Description
Datasheet