Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 612

14.4.2.11 PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2)
Address Offset: Port 0: ABAR + 12Ch
Default Value:
This is a 32-bit read-write register by which software controls SATA capabilities. Writes
to the SControl register result in an action being taken by the PCH or the interface.
Reads from the register return the last value written to it.
Bit
31:20 Reserved
19:16 Port Multiplier Port (PMP) — R/W. This field is not used by AHCI
15:12 Select Power Management (SPM) — R/W. This field is not used by AHCI
Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which
power states the PCH is allowed to transition to:
11:8
All other values reserved
Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface.
This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
7:4
The PCH Supports Gen 1 communication rates (1.5 Gb/s), Gen 2 rates
(3.0 Gb/s) and Gen 3 rates (6.0 Gb/s) (supported speeds are determined by SKU; see
Section
If software changes SPD after port has been enabled, software is required to perform a
port reset using DET=1h. This field shall remain 1h until set to another value by
software.
612
Port 1: ABAR + 1ACh
Port 2: ABAR + 22Ch (if port available; see
Port 3: ABAR + 2ACh (if port available; see
Port 4: ABAR + 32Ch
Port 5: ABAR + 3ACh
00000004h
Value Description
0h No interface restrictions
1h Transitions to the PARTIAL state disabled
2h Transitions to the SLUMBER state disabled
3h Transitions to both PARTIAL and SLUMBER states disabled
Value Description
0h No speed negotiation restrictions
1h Limit speed negotiation to Generation 1 communication rate
2h Limit speed negotiation to Generation 2 communication rate
3h Limit speed negotiation to Generation 3 communication rate
1.3)
SATA Controller Registers (D31:F2)
Attribute: R/W, RO
Section
Section
Size: 32 bits
Description
1.3)
1.3)
Datasheet