Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 665

EHCI Controller Registers (D29:F0, D26:F0)
The second set at offsets MEM_BASE + 60h to the end of the implemented register
space are implemented in the Suspend power well. Unless otherwise noted, the
suspend well registers are reset by the assertion of either of the following:
• Suspend well hardware reset
• HCRESET
16.2.2.1 USB2.0_CMD—USB 2.0 Command Register
Offset:
Default Value:
Bit
31:24 Reserved.
Interrupt Threshold Control — R/W. System software uses this field to select the
maximum rate at which the host controller will issue interrupts. The only valid values
are defined below. If software writes an invalid value to this register, the results are
undefined.
23:16
15:14 Reserved.
Asynch Schedule Update (ASC) — R/W. There is no functionality associated with this
13
bit.
Periodic Schedule Prefetch Enable — R/W. This bit is used by software to enable the
host controller to prefetch the periodic schedule even in C0.
0 = Prefetch based pause enabled only when not in C0.
1 = Prefetch based pause enable in C0.
12
Once software has written a 1b to this bit to enable periodic schedule prefetching, it
must disable prefecthing by writing a 0b to this bit whenever periodic schedule updates
are about to begin. Software should continue to dynamically disable and re-enable the
prefetcher surrounding any updates to the periodic scheduler (that is, until the host
controller has been reset using a HCRESET).
Unimplemented Asynchronous Park Mode Bits — RO. Hardwired to 000b indicating the
11:8
host controller does not support this optional feature.
Light Host Controller Reset — RO. Hardwired to 0. The PCH does not implement this
7
optional reset.
Datasheet
MEM_BASE + 20–23h
00080000h
Value Maximum Interrupt Interval
00h
01h 1 micro-frame
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames (default, equates to 1 ms)
10h 16 micro-frames (2 ms)
20h 32 micro-frames (4 ms)
40h 64 micro-frames (8 ms)
Attribute:
Size:
Description
Reserved
R/W, RO
32 bits
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