Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 704

17.1.1.46 VCiSTS—VCi Resource Status Register
®
(Intel
Address Offset: 126h–127h
Default Value:
Bit
15:2 Reserved.
1 VCi Negotiation Pending — RO. Does not apply. Hardwired to 0.
Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for
0
endpoint devices.
17.1.1.47 RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register
®
(Intel
Address Offset: 130h
Default Value:
Bit
31:20 Next Capability Offset — RO. Hardwired to 0 indicating this is the last capability.
19:16 Capability Version — RO. Hardwired to 1h.
15:0 PCI Express* Extended Capability ID — RO. Hardwired to 0005h.
17.1.1.48 ESD—Element Self Description Register
®
(Intel
Address Offset: 134h–137h
Default Value:
Bit
Port Number — RO. Hardwired to 0Fh indicating that the Intel
31:24
controller is assigned as Port #15d.
Component ID — RO. This field returns the value of the ESD.CID field of the chip
23:16
configuration section. ESD.CID is programmed by BIOS.
Number of Link Entries — RO. The Intel
15:8
device, the PCH egress port. Therefore, this field reports a value of 1h.
7:4 Reserved.
Element Type (ELTYP) — RO. The Intel
3:0
integrated Root Complex Device. Therefore, the field reports a value of 0h.
704
High Definition Audio Controller—D27:F0)
0000h
High Definition Audio Controller—D27:F0)
00010005h
High Definition Audio Controller—D27:F0)
0F000100h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
Description
Attribute:
Size:
Description
Attribute:
Size:
Description
®
High Definition Audio only connects to one
®
High Definition Audio controller is an
RO
16 bits
RO
32 bits
RO
32 bits
®
High Definition Audio
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