Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 582

14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2)
Address Offset: Primary: BAR + 04h–07h
Default Value:
Bit
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits
[31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor
31:2
Table must be Dword-aligned. The Descriptor Table must not cross a 64-K boundary in
memory.
1:0 Reserved
14.2.4 AIR—AHCI Index Register (D31:F2)
Address Offset: Primary: BAR + 10h
Default Value:
This register is available only when SCC is not 01h.
Bit
31:11 Reserved
Index (INDEX)— R/W. This Index register is used to select the Dword offset of the
10:2 Memory Mapped AHCI register to be accessed. A Dword, Word or Byte access is
specified by the active byte enables of the I/O access to the Data register.
1:0 Reserved
14.2.5 AIDR—AHCI Index Data Register (D31:F2)
Address Offset: Primary: BAR + 14h
Default Value:
This register is available only when SCC is not 01h.
Bit
Data (DATA)— R/W: This Data register is a "window" through which data is read or
written to the AHCI memory mapped registers. A read or write to this Data register
triggers a corresponding read or write to the memory mapped register pointed to by
the Index register. The Index register must be setup prior to the read or write to this
Data register.
31:0
Note that a physical register is not actually implemented as the data is actually stored
in the memory mapped registers.
Since this is not a physical register, the "default" value is the same as the default value
of the register pointed to by Index.
582
Secondary: BAR + 0Ch
All bits undefined
00000000h
All bits undefined
SATA Controller Registers (D31:F2)
Attribute: R/W
0Fh
–
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
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