Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 456

13.1.17 SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0)
Offset Address: 64h
Default Value:
Lockable:
Bit
Serial IRQ Enable (SIRQEN) — R/W.
7
0 = The buffer is input only and internally SERIRQ will be a 1.
1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.
Serial IRQ Mode Select (SIRQMD) — R/W.
0 = The serial IRQ machine will be in quiet mode.
1 = The serial IRQ machine will be in continuous mode.
6
NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for
Serial IRQ Frame Size (SIRQSZ) — RO. Fixed field that indicates the size of the
5:2
SERIRQ frame as 21 frames.
Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the
SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In
continuous mode, the PCH will drive the start frame for the number of clocks specified.
In quiet mode, the PCH will drive the start frame for the number of clocks specified
minus one, as the first clock was driven by the peripheral.
1:0
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
456
10h
No
at least one frame after coming out of reset before switching back to Quiet
Mode. Failure to do so will result in the PCH not recognizing SERIRQ interrupts.
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W, RO
Size: 8 bit
Power Well: Core
Description
Datasheet