Intel 82801EB Programmer's Reference Manual
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Intel 82801EB Programmer's Reference Manual

Intel 82801EB Programmer's Reference Manual

Serial ata controller
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®
Intel
82801EB (ICH5) and
®
Intel
82801ER (ICH5R)
Serial ATA Controller
Programmer's Reference Manual (PRM)
July 2003
Document Number: 252671-002

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  • Page 1 ® Intel 82801EB (ICH5) and ® Intel 82801ER (ICH5R) Serial ATA Controller Programmer’s Reference Manual (PRM) July 2003 Document Number: 252671-002...
  • Page 2 The Intel® ICH5 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

  • Page 3: Table Of Contents

    4.4.2 Device Detection – Software Examples..........28 ATA Swap Bay Support ..................28 ® Implementing the Intel ICH5 SATA Host Controller in ACPI Namespace ..29 Appendix A – Coding Examples ......................31 Enabling/Disabling SATA Ports from a WDM Driver ..........31 Enabling/Disabling SATA Ports in the _PSx Control Method .......
  • Page 4 Figure 9. Power-on to Device Ready Elapsed Time ............27 Tables ® Table 1. Intel ICH5 Device IDs ..................7 Table 2. Valid BIOS Option for the Programming Interface Register........ 22 Table 3. Illegal BIOS Options for the Programming Interface Register ......22...
  • Page 5 Revision History Revision Description Revision Date Number -001 Initial Release April 2003 -002 Updated register/bit names to match Intel® 82801EB I/O Controller July 2003 Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R) Datasheet SATA Programmer’s Reference Manual...
  • Page 6 This page is intentionally left blank. SATA Programmer’s Reference Manual...

  • Page 7: Introduction

    This document will be supplemented from time to time with specification updates. The specification updates contain information relating to the latest programming changes. Check with your Intel representative for availability of specification updates.
  • Page 8 Introduction This page is intentionally left blank. SATA Programmer’s Reference Manual...

  • Page 9: Conventions

    Conventions Conventions Register Access This document uses the following notation as related to register access: RegOffset.BitOffset. Where: RegOffset specifies the name of the register to be accessed (either in I/O or PCI configuration space) BitOffset specifies the name of a bit contained within RegOffset that is to be accessed. Example (Uses the Class Code register defined in the table below): Assumes the following standard PCI configuration register (Class Code) with CC.SCC refers to the Sub Class Code (SCC - bits 0:7) implemented within the Class Code (CC –...
  • Page 10 Conventions This page is intentionally left blank. SATA Programmer’s Reference Manual...

  • Page 11: Intel ® Ich Sata Controller Basic Attributes

    Intel® ICH SATA Controller Basic Attributes ® Intel ICH SATA Controller Basic Attributes The register set for the ICH5 SATA controller is basically identical to that of the integrated parallel ATA controller. Because the underlying SATA functionality is transparent to operating system software, it need not have any special knowledge about SATA or SATA devices.

  • Page 12: Host Controller Configurations

    Intel® ICH SATA Controller Basic Attributes Host Controller Configurations The SATA host controller can function independently of, or in conjunction with the parallel ATA (P-ATA) host controller. The ICH5 can support a maximum of six ATA devices: four parallel ATA device plus two serial ATA devices.

  • Page 13: Theory Of Operation

    Theory of Operation Theory of Operation This section describes the proper usage and programming of the SATA host controller by BIOS and the operating system when the host controller is operating in compatible or enhanced configuration. Compatible Configuration The compatible configuration is for the express purpose of maintaining backward-compatibility with those operating systems that do not comprehend native mode of operation.

  • Page 14: Additional Register Support

    Theory of Operation 4.1.1 Additional Register Support Support of certain Compatible configuration options requires that the ICH5 implement an additional hardware register that is configurable via BIOS. This register is located in the SATA function’s PCI configuration space at offset 90h and is defined below. The usage model for this register is described in subsequent sections.

  • Page 15: Compatible Configuration - Option 1

    SATA ports, but will not be accessible to software. Figure 1 illustrates this configuration: Figure 1. Compatible Configuration - Option 1 Port 0 S-ATA Port 1 ® Intel ICH5 Primary P-ATA Secondary Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to software.

  • Page 16: Compatible Configuration - Option 2

    BIOS Selectable S-ATA Logical Secondary Port 1 ® Intel ICH5 P-ATA Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to software. Note: In this configuration, software reads and writes to the slave device registers will result in a master abort and as such reading from the slave device registers will return all 1.

  • Page 17: Compatible Configuration - Option 3 (Combined)

    Figure 3. Compatible Configuration - Option 3 Viewed as a single logical channel Port 0 S-ATA Port 1 Logical Primary/Secondary Channel Assignment Intel® ICH5 are BIOS Selectable Physical Primary/Secondary P-ATA Channels are Mutually Exclusive SATA Programmer’s Reference Manual...

  • Page 18: Figure 4. Compatible Configuration - Option 3A

    Figure 4. Compatible Configuration - Option 3a Port 0 Logical Primary S-ATA Channel Port 1 Intel® ICH5 Physical Primary Channel Not Used P-ATA Logical Secondary Channel Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to software.

  • Page 19: Figure 5. Compatible Configuration - Option 3B

    Theory of Operation Figure 5. Compatible Configuration - Option 3b Port 0 Loical Primary S-ATA Channel Port 1 Intel® ICH5 Physical Primary Channel Not Used P-ATA Logical Secondary Channel Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to software.

  • Page 20: Enhanced Configuration

    Theory of Operation Figure 7. Compatible Configuration - Option 3d Port 0 Logical Secondary S-ATA Channel Port 1 Intel® ICH5 Logical Primary Channel P-ATA Physical Secondary Channel Not Used Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to software.

  • Page 21: Pi - Programming Interface Register - Offset 09H

    ICH5 P-ATA Note: While the enhanced configuration can support a maximum of six ATA devices, Intel recommends that its customers limit their platforms to a four-device maximum configuration (applicable to both compatible and enhanced configuration), as this will provide for an easier transition to a four SATA device maximum configuration on future ICHs.

  • Page 22: Table 2. Valid Bios Option For The Programming Interface Register

    Theory of Operation Table 2 illustrates the valid values that system BIOS can use for the programming interface register when in enhanced mode. Note: The ICH5 does permit the SATA and P-ATA host controllers to simultaneously operate in native mode if they are programmed to do so by the operating system. Due to potential operating system incompatibilities, it is a requirement (when in enhanced mode) that the system BIOS programs the P-ATA and SATA host controllers exactly as described in Table 2.

  • Page 23: Map Register Programming

    Theory of Operation 4.2.2 MAP Register Programming As shown in Figure 8. Enhanced Configuration, enhanced mode configures the SATA so each SATA port is viewed as individual logical channels with a single master device. Using the MAP register, the logical SATA channels can be configured so that port 0 is the logical primary channel and port 1 is the logical secondary channel or vice-versa.

  • Page 24: Port Enabling/Disabling

    Theory of Operation 4.3.1.1 Port Enabling/Disabling By default, the SATA ports are set (by hardware) to the disabled state as a result of a D3 to D0 power state transition (due to initial power-on reset or resume from suspend). System software may choose to (keep) disable a port as a result of a device being disconnected from a port(s).

  • Page 25: Enabling/Disabling A Sata Port From An Operating System Driver

    Theory of Operation 4.3.1.1.2 Enabling/Disabling a SATA Port from an Operating System Driver To disable or enable a SATA port, system software need only program the PCS.PxE (where x is 0 for Port 0 or 1 for Port 1) bit(s) with a 0 or a 1. Note that the SATA host controller hardware allows the PCS.PxE bits to be written to individually or simultaneously.

  • Page 26: Device Presence Detect

    Theory of Operation Device Presence Detect The ICH5 SATA host controller provides bits in the PCS register (P0P and P1P) that can be used by system software to detect the presence of (or lack of) SATA device(s) connected to the SATA host controller.

  • Page 27: Figure 9. Power-On To Device Ready Elapsed Time

    Theory of Operation Figure 9. Power-on to Device Ready Elapsed Time Device Ready BSY == 0 Power System SW SATA HW DRDY == 1 sets PxE sets PxP Time us or ms or secs secs In Figure 9, the total elapsed time from power on until a device attached to a SATA port is “ready.”...

  • Page 28: Device Detection - Software Examples

    Theory of Operation The accuracy of the PxP bits cannot be guaranteed if the SATA PHY and associated device is in a slumber state. System software shall first disable the port and then re-enable it. This will cause the SATA PHY and associated device to wake, thus allowing the SATA hardware to properly detect and report the port connect status.

  • Page 29: Implementing The Intel ® Ich5 Sata Host Controller In Acpi Namespace

    Theory of Operation ® Implementing the Intel ICH5 SATA Host Controller in ACPI Namespace See Appendix B – Example ACPI Namespace for an example of an ACPI namespace for the ICH5 SATA host controller. This example supports the ICH5 SATA host controller operating in enhanced, combined and non-combined modes.
  • Page 30 Theory of Operation This page is intentionally left blank. SATA Programmer’s Reference Manual...

  • Page 31: Appendix A - Coding Examples

    Theory of Operation Appendix A – Coding Examples Enabling/Disabling SATA Ports from a WDM Driver // Function Proto for Reading and Writing to device configuration space NTSTATUS ReadWriteConfigSpace( PDEVICE_OBJECT pDO, BOOLEAN fRead, PVOID pBuf, ULONG Offset, ULONG Length); // This example illustrates how a WDM driver could read/write the PCS.PxE bits for // enabling or disabling the SATA port(s).
  • Page 32 Theory of Operation // need to perform a read/write modified in order to do this // properly // Read the current settings ReadWriteConfigSpace( pDO, TRUE, &val, 0x92, sizeof( val)); val |= 1; // set bit 0 to enable Port 0 ReadWriteConfigSpace( pDO, FALSE, &val, 0x92, sizeof( val));...

  • Page 33: Enabling/Disabling Sata Ports In The _Psx Control Method

    Theory of Operation nextStack->Parameters.ReadWriteConfig.Buffer = pBuf; nextStack->Parameters.ReadWriteConfig.Offset = Offset; nextStack->Parameters.ReadWriteConfig.Length = Length; status = IoCallDriver( pDO, irp); if( status == STATUS_PENDING) { // Request did not complete. Need to wait until it does KeWaitForSingleObject( &event, Suspended, KernelMode, FALSE, NULL); status = pIrp->IoStatus.Status; return( status);...
  • Page 34 Theory of Operation // simultaneously if necessary Method( EPRT, 1) { Store( 1, Local0) // Set max attempts Store( Arg0, Local1) While( LNotEqual( Local0, 0)){ Or( Arg0, PCS, PCS) // enable Port(s) Sleep( 500) // Wait 500ms. Some devices respond // very quickly, some longer.
  • Page 35 Theory of Operation // depending on which port is configured as primary and secondary Device( DRV0) // Logical primary master Name( _ADR, 0) … // Handle transitions to D0 power state Method(_PS0,0) // make sure the OS drivers finds the ports in an enabled state as they // (the device drivers) may have been designed for P-ATA and ‘know’...
  • Page 36 Theory of Operation // we need to disable the SATA ports here // Since enhance mode implements a master-master scheme, only 1 port // would be disabled here (dependent on the MAP settings). In Combined // mode, both SATA ports are viewed as a single logical channel // implementing a master-slave configuration in which case both ports are // disabled.

  • Page 37: Device Presence Check - Using I/O

    Theory of Operation … // power plane control is platform specific // Must wait 30ms before we can enable the ports Sleep( 30) EPRT( 0x03) // enable the ports, assumes combined mode // Check ports and disable device power plane if port(s) not enabled. …...
  • Page 38 Theory of Operation BYTE bMAP = OS_ReadPCI( 0x90); // read the map register // It is assumed that the port is enabled and the device and PHY are not in a // slumber state as this is required in order for the port presence bits to be // accurate.

  • Page 39: Device Presence Check - Using Acpi

    Theory of Operation // At this point, iAllStatus will contain: // 0 ==> no devices present // 1 ==> master device present // 2 ==> slave device present // -1 ==> Not supported or unknown (P-ATA) return( iAllStatus); // done Device Presence Check –...
  • Page 40 Theory of Operation #define SATA_GET_PORT_STATUS 'SPSG' // Control method to execute // SATA_CheckPortStatus - Get the SATA port status // Entry: ==> pointer to our physical device object pdwStatus ==> ptr to receive port status value // Exit: Returns status code. If success, pdwStatus has the SATA port status: 0 ==>...
  • Page 41 Theory of Operation // if not successful, the control method probably does not // exists or APM mode is being used if( NT_SUCCESS( status)) { // make sure we received the correct data type back if( pOutputBuffer->Argument[ 0].Type != ACPI_METHOD_ARGUMENT_INTEGER) status = STATUS_DATA_ERROR;...
  • Page 42 Theory of Operation Irp = IoBuildDeviceIoControlRequest( Ioctl, Pdo, InputBuffer, InputSize, OutputBuffer, OutputSize, FALSE, &evIoctl, &ioBlock); if( !Irp) status = STATUS_INSUFFICIENT_RESOURCES; else { pIrpStack = IoGetNextIrpStackLocation( Irp); pIrpStack->MajorFunction = IRP_MJ_DEVICE_CONTROL; // Pass the request to the Pdo, always wait for the completion // routine status = IoCallDriver( Pdo, Irp);...

  • Page 43: Acpi Control Method (Gsps)

    Theory of Operation ACPI Control Method (GSPS) // Define where the SATA MAP and Status/Control registers reside in PCI Config // space OperationRegion(IDEC,PCI_Config,0x90,3) Field(IDEC,ByteAcc,NoLock,Preserve) MAP, 8, // SATA Map register - Offset 90h , 8, // skip 8 bits PCS, 8 // SATA Port status and control register - Offset 92h Device( IDE1) { // SATA controller Name(_ADR, 0x01f0002)
  • Page 44 Theory of Operation Store( MAP, Local1) Store( PCS, Local2) // make sure the P-ATA is not the primary channel If( LLess( Local1, 0x06)) // Not P-ATA device. Must be SATA. Store( Zero, Local3) Store( Zero, Local4) Store( Zero, Local5) If( LAnd( Local2, 0x10)) Store( One, Local3) // Port 0 device present If( LAnd( Local2, 0x20)) Store( One, Local4) // Port 1 device present...
  • Page 45 Theory of Operation return( 0xffffffff) Device( DRV0) // Logical primary master Name( _ADR, 0) Device( SECD) // Secondary channel Method( GSPS, 0) // Get the port status // Similar to GSPS for PRID Name( _ADR, 1) // Logical secondary channel (Port 0 or 1, BIOS selectable) Device( DRV0) // Logical secondary master Name(_ADR, 0) SATA Programmer’s Reference Manual...
  • Page 46 Theory of Operation This page is intentionally left blank. SATA Programmer’s Reference Manual...

  • Page 47: Appendix B - Example Acpi Namespace

    Theory of Operation Appendix B – Example ACPI Namespace // The following illustrates the sample ASL code for a Combined // and non-combined mode configuration. // The SATA controller supports several configurations. Combined // mode and non-Combined mode. If in non-Combined mode (P-ATA and // SATA are separate PCI functions), then: Port 0 == logical primary master Port 1 == logical secondary master...
  • Page 48 Theory of Operation P-ATA == primary master/slave Port 0 == secondary slave Port 1 == secondary master OperationRegion(IDEC,PCI_Config,0x90,3) Field(IDEC,ByteAcc,NoLock,Preserve) MAP, 8, // SATA Map register - Offset 90h , 8, // Skip 8 bits PCS, 8 // SATA Port status and control register Device( IDE1) { // SATA controller Name(_ADR, 0x01f0002) // Device 31, Function 2...
  • Page 49 Theory of Operation // Since a device detect failed, we disable the port. This is not // required, but is part of a good power conservation policy. And( PCS, 0x02, PCS) // disable Port 0 // Check if we are enabling Port 1 If( LAnd( Arg0, 0x02) { If( LAnd( Local2, 0x20)) { Decrement( Local1)
  • Page 50 Theory of Operation Method( CTYP, 1) Store( Zero, Local0) If( Arg0) // Check the Primary Channel // Check if combined mode and if this device is a P-ATA // device MAP == 100b or 101b Combined mode, P-ATA is // secondary If( LAnd( LGreater( MAP, 0x1), LLess( MAP, 0x6))) Store( 0x1, Local0) // SATA is primary, combined Else {...
  • Page 51 Theory of Operation If( LEqual( MAP, One) Store( 6, Local0) // port 1 is secondary master Return( Local0) // Logical Primary channel // Physical SATA Port 0 == logical primary master // Physical SATA Port 1 == logical primary master // In Combined mode, the following must be supported by PRID: // Physical SATA Port 0 == logical primary master // Physical SATA Port 1 == logical primary slave...
  • Page 52 Theory of Operation // PCS register // Since Enhance mode implements a master-master // scheme, only 1 port would be enabled here (dependent // on the MAP settings). In Combined mode, both SATA // ports are viewed as a single logical channel // implementing a master-slave configuration in which // case both ports are enabled.
  • Page 53 Theory of Operation // Not P-ATA device. Must be SATA // make sure the OS drivers finds the ports in an enabled // state as they (the device drivers) may have been // designed for P-ATA and 'know' nothing about the PCS // register // Since Enhance mode implements a master-master scheme, // only 1 port would be disabled here (dependent on the...
  • Page 54 Theory of Operation // device, a check may need to be added since the task file // could be different. Method( _GTF,0) // return task file info based on device type If( CTYP( 0)) // Is Combined mode and is a P-ATA device ..
  • Page 55 Theory of Operation //******************************************************* // Logical Secondary channel // Physical SATA Port 0 == logical secondary master // Physical SATA Port 1 == logical secondary master // In Combined mode, the following must be supported by SECD: // Physical SATA Port 0 == logical secondary master // Physical SATA Port 1 == logical secondary slave // Physical SATA Port 0 == logical secondary slave // Physical SATA Port 1 == logical secondary master...
  • Page 56 Theory of Operation // Since Enhance mode implements a master-master scheme, // only 1 port would be enabled here (dependent on the // MAP settings). In Combined mode, both SATA ports are // viewed as a single logical channel implementing a // master-slave configuration in which case both ports // are enabled.
  • Page 57 Theory of Operation // enabled state as they (the device drivers) may have // been designed for P-ATA and 'know' nothing about the // PCS register // Since Enhance mode implements a master-master scheme, // only 1 port would be disabled here (dependent on the // MAP settings).
  • Page 58 Theory of Operation Method( _GTF,0) // return task file info based on device type If( CTYP( 1)) // Is Combined mode and is a P-ATA device ..Else // Not P-ATA device. Must be SATA ..//******************************************************* // DRV1 is only accessed when configured for Combined mode. In // non-Combined mode SATA devices use a master-master // arrangement.
  • Page 59 Theory of Operation //******************************************************* SATA Programmer’s Reference Manual...

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