Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 927

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.9.14 PID—PCI Power Management Capability ID Register
(KT—D22:F3)
Address Offset: C8–C9h
Default Value:
Bit
15:8
7:0
23.9.15 PC—PCI Power Management Capabilities ID Register
(KT—D22:F3)
Address Offset: CA–CBh
Default Value:
Bit
15:11
10:6
5
4
3
2:0
23.9.16 MID—Message Signaled Interrupt Capability ID
Register (KT—D22:F3)
Address Offset: D0–D1h
Default Value:
Message Signalled Interrupt is a feature that allows the device/function to generate an
interrupt to the host by performing a DWORD memory write to a system specified
address with system specified data. This register is used to identify and configure an
MSI capable device.
Bit
15:8
7:0
Datasheet
D001h
Next Capability (NEXT)— RO. A value of D0h points to the MSI capability.
Cap ID (CID)— RO. This field indicates that this pointer is a PCI power
management.
0023h
PME Support (PME)— RO.This field indicates no PME# in the PT function.
Reserved
Device Specific Initialization (DSI)— RO. This bit indicates that no device-specific
initialization is required.
Reserved
PME Clock (PMEC)— RO. This bit indicates that PCI clock is not required to generate
PME#
Version (VS)— RO. This field indicates support for the PCI Power Management
Specification, Revision 1.2.
0005h
Next Pointer (NEXT)— RO. This value indicates this is the last item in the list.
Capability ID (CID)— RO. This field value of Capabilities ID indicates device is
capable of generating MSI.
Attribute: RO
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
927