Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 785

PCI Express* Configuration Registers
19.1.45 PMCAP—Power Management Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A0h
Default Value:
Bit
15:8
7:0
19.1.46 PMC—PCI Power Management Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A2h
Default Value:
Bit
15:11
10
9
8:6
5
4
3
2:0
Datasheet
A1h
–
0001h
Next Capability (NEXT) — RO. Indicates this is the last item in the list.
Capability Identifier (CID) — RO. Value of 01h indicates this is a PCI power
management capability.
A3h
–
C802h
PME_Support (PMES) — RO. Indicates PME# is supported for states D0, D3
D3 . The root port does not generate PME#, but reporting that it does is necessary
COLD
for some legacy operating systems to enable PME# in devices connected behind this
root port.
D2_Support (D2S) — RO. The D2 state is not supported.
D1_Support (D1S) — RO The D1 state is not supported.
Aux_Current (AC) — RO. Reports 375 mA maximum suspend well current required
when in the D3 state.
COLD
Device Specific Initialization (DSI) — RO.
1 = Indicates that no device-specific initialization is required.
Reserved
PME Clock (PMEC) — RO.
1 = Indicates that PCI clock is not required to generate PME#.
Version (VS) — RO. Indicates support for Revision 1.1 of the PCI Power Management
Specification.
Attribute: RO
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
and
HOT
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