Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 926

23.9.10 SVID—Subsystem Vendor ID Register (KT—D22:F3)
Address Offset: 2Ch
Default Value:
Bit
15:0
23.9.11 SID—Subsystem ID Register (KT—D22:F3)
Address Offset: 2Eh
Default Value:
Bit
15:0
23.9.12 CAP—Capabilities Pointer Register (KT—D22:F3)
Address Offset: 34h
Default Value:
This optional register is used to point to a linked list of new capabilities implemented by
the device.
Bit
7:0
23.9.13 INTR—Interrupt Information Register (KT—D22:F3)
Address Offset: 3C–3Dh
Default Value:
Bit
15:8
7:0
926
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
2Dh
–
0000h
Subsystem Vendor ID (SSVID) — R/WO. Indicates the sub-system vendor
identifier. This field should be programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a DWord write with SID register.
2Fh
–
8086h
Subsystem ID (SSID) — R/WO. Indicates the sub-system identifier. This field should
be programmed by BIOS during boot-up. Once written, this register becomes Read
Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a DWord write with SVID register.
C8h
Capability Pointer (CP)— RO. This field indicates that the first capability pointer is
offset C8h (the power management capability).
0200h
Interrupt Pin (IPIN)— RO. A value of 1h/2h/3h/4h indicates that this function
implements legacy interrupt on INTA/INTB/INTC/INTD, respectively
FunctionValueINTx
(3 KT/Serial Port)02hINTB
Interrupt Line (ILINE)— R/W. The value written in this register tells which input of
the system interrupt controller, the device's interrupt pin is connected to. This value
is used by the OS and the device driver, and has no affect on the hardware.
Attribute: R/WO
Size: 16 bits
Description
Attribute: R/WO
Size: 16 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/W, RO
Size: 16 bits
Description
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