Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 410

10.1.80 USBOCM1—Overcurrent MAP Register 1
Offset Address: 35A0–35A3h
Default Value:
All bits in this register are in the Resume Well and is only cleared by RSMRST#.
Bit
31:24
23:16
15:8
7:0
410
C0300C03h
OC3 Mapping Each bit position maps OC3# to a set of ports as follows: The OC3#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port's bit map is set only for one
OC pin.
Bit 31 30 29
Port 7 6 5
OC2 Mapping Each bit position maps OC2# to a set of ports as follows: The OC2#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port's bit map is set only for one
OC pin.
Bit 23 22 21
Port 7 6 5
OC1 Mapping Each bit position maps OC1# to a set of ports as follows: The OC1#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port's bit map is set only for one
OC pin.
Bit 15 14 13
Port 7 6 5
OC0 Mapping Each bit position maps OC0# to a set of ports as follows: The OC0#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port's bit map is set only for one
OC pin.
Bit 7 6 5
Port 7 6 5
Chipset Configuration Registers
Attribute:
Size:
Description
28 27 26 25
4 3 2 1
20 19 18 17
4 3 2 1
12 11 10 9
4 3 2 1
4 3 2 1
4 3 2 1
R/W0
32-bit
24
0
16
0
8
0
0
0
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