Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 428

Bit
Maximum Delayed Transactions (MDT) — R/W. Controls the maximum number of
delayed transactions that the PCH PCI bridge will run. Encodings are:
00 =) 2 Active, 5 pending
7:6
01 =) 2 active, no pending
10 =) 1 active, no pending
11 =) Reserved
5 Reserved
Auto Flush After Disconnect Enable (AFADE) — R/W.
0 = The PCI bridge will retain any fetched data until required to discard by producer/
4
1 = The PCI bridge will flush any prefetched data after either the PCI master (by
Never Prefetch (NP) — R/W.
0 = Prefetch enabled
3
1 = The PCH will only fetch a single DW and will not enable prefetching, regardless of
Memory Read Multiple Prefetch Disable (MRMPD) — R/W.
0 = MRM commands will fetch multiple cache lines as defined by the prefetch
2
1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte
Memory Read Line Prefetch Disable (MRLPD) — R/W.
0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm.
1
1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned
Memory Read Prefetch Disable (MRPD) — R/W.
0
0 = MR commands will fetch up to a 64-byte aligned cache line.
1 = Memory read (MR) commands will fetch only a single DW.
428
consumer rules.
deasserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI
transfer.
the command being an Memory read (MR), Memory read line (MRL), or Memory
read multiple (MRM).
algorithm.
aligned cache line.
cache line.
PCI-to-PCI Bridge Registers (D30:F0)
Description
Datasheet