Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 732

17.1.2.44 SDBDPL—Stream Descriptor Buffer Descriptor List
Pointer Lower Base Address Register
®
(Intel
Memory Address:Input Stream[0]: HDBAR + 98h
Default Value:
Bit
Buffer Descriptor List Pointer Lower Base Address — R/W. Lower address of the
31:7 Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA
transfer may be corrupted.
6:0 Hardwired to 0 forcing alignment on 128-B boundaries.
17.1.2.45 SDBDPU—Stream Descriptor Buffer Descriptor List
Pointer Upper Base Address Register
®
(Intel
Memory Address:Input Stream[0]: HDBAR + 9Ch
Default Value:
Bit
Buffer Descriptor List Pointer Upper Base Address — R/W. Upper 32-bit address
31:0 of the Buffer Descriptor List. This value should only be modified when the RUN bit is 0,
or DMA transfer may be corrupted.
732
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + B8h
Input Stream[2]: HDBAR + D8h
Input Stream[3]: HDBAR + F8h
Output Stream[0]: HDBAR + 118h
Output Stream[1]: HDBAR + 138h
Output Stream[2]: HDBAR + 158h
Output Stream[3]: HDBAR + 178h
00000000h
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + BCh
Input Stream[2]: HDBAR + DCh
Input Stream[3]: HDBAR + FCh
Output Stream[0]: HDBAR + 11Ch
Output Stream[1]: HDBAR + 13Ch
Output Stream[2]: HDBAR + 15Ch
Output Stream[3]: HDBAR + 17Ch
00000000h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Description
Attribute:R/W
Size: 32 bits
Description
R/W,RO
Size: 32 bits
Datasheet