Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 455

LPC Interface Bridge Registers (D31:F0)
13.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQA
Default Value:
Lockable:
Bit
7
6:4
3:0
Datasheet
60h, PIRQB
–
PIRQC 62h, PIRQD
–
80h
No
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts
specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS
when setting up for I/O APIC interrupt delivery mode.
Reserved
IRQ Routing — R/W. (ISA compatible.)
Value IRQ
0000b Reserved
0001b Reserved
0010b Reserved
0011b IRQ3
0100b IRQ4
0101b IRQ5
0110b IRQ6
0111b IRQ7
61h, Attribute:R/W
–
63h
–
Size:8 bit
Power Well:Core
Description
Value IRQ
1000b Reserved
1001b IRQ9
1010b IRQ10
1011b IRQ11
1100b IRQ12
1101b Reserved
1110b IRQ14
1111b IRQ15
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