Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 764

19.1.12 BNUM—Bus Number Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 18–1Ah
Default Value:
Bit
23:16
15:8
7:0
19.1.13 SLT—Secondary Latency Timer
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 1Bh
Default Value:
Bit
7:0
19.1.14 IOBL—I/O Base and Limit Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 1Ch–1Dh
Default Value:
Bit
15:12
11:8
7:4
3:0
764
000000h
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number
below the bridge.
Secondary Bus Number (SCBN) — R/W. Indicates the bus number the port.
Primary Bus Number (PBN) — R/W. Indicates the bus number of the backbone.
00h
Secondary Latency Timer — Reserved for a Root Port per the PCI Express* Base
Specification.
0000h
I/O Limit Address (IOLA) — R/W. I/O Base bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
I/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not
support 32-bit I/O addressing.
I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Base Address Capability (IOBC) — RO. Indicates that the bridge does not
support 32-bit I/O addressing.
PCI Express* Configuration Registers
Attribute: R/W
Size: 24 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/W, RO
Size: 16 bits
Description
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