Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 795

PCI Express* Configuration Registers
Bit
Data Link Protocol Error Mask (DLPE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
4
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
3:1 Reserved
0 Training Error Mask (TE) — RO. Training Errors not supported
19.1.56 UEV — Uncorrectable Error Severity
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 10Ch
Default Value:
Bit
31:21 Reserved
Unsupported Request Error Severity (URE) — R/W.
20
0 = Error considered non-fatal. (Default)
1 = Error is fatal.
19 ECRC Error Severity (EE) — RO. ECRC is not supported.
Malformed TLP Severity (MT) — R/W.
18
0 = Error considered non-fatal.
1 = Error is fatal. (Default)
Receiver Overflow Severity (RO) — R/W.
17
0 = Error considered non-fatal.
1 = Error is fatal. (Default)
16 Reserved
Completion Abort Severity (CA) — R/W.
15
0 = Error considered non-fatal. (Default)
1 = Error is fatal.
14 Reserved
Flow Control Protocol Error Severity (FCPE) — RO. Flow Control Protocol Errors not
13
supported.
Poisoned TLP Severity (PT) — R/W.
12
0 = Error considered non-fatal. (Default)
1 = Error is fatal.
11:5 Reserved
Data Link Protocol Error Severity (DLPE) — R/W.
4
0 = Error considered non-fatal.
1 = Error is fatal. (Default)
3:1 Reserved
0 Training Error Severity (TE) — R/W. TE is not supported.
Datasheet
enabled.
masked.
10Fh
–
00060011h
Description
Attribute: RO, R/W
Size: 32 bits
Description
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