Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 614

Hide thumbs Also See for 6 SERIES CHIPSET - DATASHEET 01-2011:
Table of Contents

Advertisement

Bit
CRC Error (C) — R/WC. Indicates that one or more CRC errors occurred with the Link
21
Layer.
20
Disparity Error (D) — R/WC. This field is not used by AHCI.
10b to 8b Decode Error (B) — R/WC. Indicates that one or more 10b to 8b decoding
19
errors occurred.
Comm Wake (W) — R/WC. Indicates that a Comm Wake signal was detected by the
18
Phy.
17
Phy Internal Error (I) — R/WC. Indicates that the Phy detected some internal error.
PhyRdy Change (N) — R/WC. When set to 1, this bit indicates that the internal
PhyRdy signal changed state since the last time this bit was cleared. In the PCH, this bit
16
will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then
reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if
enabled. Software clears this bit by writing a 1 to it.
15:12
Reserved
Internal Error (E) — R/WC. The SATA controller failed due to a master or target abort
11
when attempting to access system memory.
Protocol Error (P) — R/WC. A violation of the Serial ATA protocol was detected.
10
NOTE: The PCH does not set this bit for all protocol violations that may occur on the
Persistent Communication or Data Integrity Error (C) — R/WC. A communication
error that was not recovered occurred that is expected to be persistent. Persistent
9
communications errors may arise from faulty interconnect with the device, from a
device that has been removed or has failed, or a number of other causes.
Transient Data Integrity Error (T) — R/WC. A data integrity error occurred that was
8
not recovered by the interface.
7:2
Reserved.
Recovered Communications Error (M) — R/WC. Communications between the
device and host was temporarily lost but was re-established. This can arise from a
1
device temporarily being removed, from a temporary loss of Phy synchronization, or
from other causes and may be derived from the PhyNRdy signal between the Phy and
Link layers.
Recovered Data Integrity Error (I) — R/WC. A data integrity error occurred that
0
was recovered by the interface through a retry operation or other recovery action.
614
SATA link.
SATA Controller Registers (D31:F2)
Description
Datasheet

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

6 series

Table of Contents