Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 100

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 6 of 6)
Signal Name
DDP[D:B]_[3:0]P,
DDP[D:B]_[3:0]N
DDP[D:B]_AUXP,
DDP[D:B]_AUXN
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPC_CTRLCLK,
DDPD_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLDATA
NOTES:
1. The states of Core and processor signals are evaluated at the times During PLTRST# and
Immediately after PLTRST#. The states of the Controller Link signals are taken at the
times during CL_RST1# and Immediately after CL_RST1#. The states of the Suspend
signals are evaluated at the times during RSMRST# and Immediately after RSMRST#, with
an exception to GPIO signals; refer to
reset. The states of the HDA signals are evaluated at the times During HDA_RST# and
Immediately after HDA_RST#.
2. SLP_S5# signal will be high in the S4 state and low in the S5 state.
3. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset
HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be
Running.
4. PETp/n[8:1] low until port is enabled by software.
5. The SLP_A# state will be determined by Intel ME Policies.
6. The state of signals in S3-5 will be defined by Intel ME Policies.
7. This signal is sampled as a functional strap during reset. Refer to Functional straps
definition table for usage.
8. SLP_LAN# behavior after reset is dependent on value of SLP_LAN# default value bit. A
soft-strap is used to select between SLP_LAN# and GPIO usage. When strap is set to 0
(default), pin is used as SLP_LAN#; when soft-strap is set to 1, pin is used as GPIO29.
9. Native functionality multiplexed with these GPIOs are not used in Desktop Configurations.
10. Native/GPIO functionality controlled using soft straps. Default to Native functionality until
soft straps are loaded.
11. State of the pins depend on the source of VccASW power.
12. Pin is tri-stated prior to APWROK assertion during Reset.
13. When Controller Reset Bit of Global Control Register (D27:F0 Offset HDBAR 08h bit 0) gets
set, this pin will start toggling.
14. Not all signals or pin functionalities may be available on a given SKU. See
Chapter 2
15. Controller Link Clock and Data buffers use internal pull-up and pull-down resistors to drive
a logical 1 or a 0.
100
Power During
1
Plane Reset
Digital Display Interface
Core Low
Core Low
Core High-Z
Core Low
Core High-Z
Core Low
for details.
Immediately
S0/S1
1
after Reset
Low Defined
Low Defined
High-Z Defined
High-Z Defined
High-Z Defined
High-Z Defined
Section 2.24 for more details on GPIO state after
PCH Pin States
S3 S4/S5
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Section 1.3 and
Datasheet