Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 384

Hide thumbs Also See for 6 SERIES CHIPSET - DATASHEET 01-2011:
Table of Contents

Advertisement

10.1.37
D22IP—Device 22 Interrupt Pin Register
Offset Address: 3124–3127h
Default Value:
Bit
31:16
15:12
11:8
7:4
3:0
384
00000001h
Reserved
KT Pin (KTIP) — R/W. Indicates which pin the Keyboard text PCI functionality drives
as its interrupt
0h = No Interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
IDE-R Pin (IDERIP) — R/W. Indicates which pin the IDE Redirect PCI functionality
drives as its interrupt
0h = No Interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
®
Intel
MEI #2 Pin (MEI2IP) — R/W. Indicates which pin the Management Engine
Interface #2 drives as its interrupt
0h = No Interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
®
Intel
MEI #1 Pin (MEI1IP) — R/W. Indicates which pin the Management Engine
Interface controller #1 drives as its interrupt
0h = No Interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Chipset Configuration Registers
Attribute:
R/W
Size:
32-bit
Description
Datasheet

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

6 series

Table of Contents