Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 102

Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 2 of 6)
Signal Name
19
CLKRUN#
PLTRST# Suspend
5
SLP_A# Suspend
SLP_S3# Suspend
SLP_S4# Suspend
SLP_S5#/GPIO63 Suspend
SUS_STAT#/GPIO61 Suspend
SUSCLK/GPIO62 Suspend
SUSWARN#/
SUSPWRDNACK/ Suspend
GPIO30 (note 20)
SUSWARN#/
SUSPWRDNACK/ Suspend
GPIO30 (note 21)
DRAMPWROK Suspend
LAN_PHY_PWR_CTRL
Suspend
9
/GPIO12
PMSYNCH
STP_PCI#/GPIO34
14
SLP_LAN# /GPIO29
SLP_LAN# (using
soft-strap) Suspend
GPIO29 (using soft-
strap)
PROCPWRGD Processor
SMBCLK, SMBDATA Suspend
102
Power During Immediately
1
Plane Reset
Power Management
Core Low
Low
Low
Low
Low
Low
Low
Low
0
0
Low
Low
Core Low
High-Z
Core High-Z (Input)
(Input)
Low
Low
Processor Interface
Low
SMBus Interface
High-Z
C-x
1
after Reset states
Low Defined
High High
High High
High High
High High
High High
High High
1 Defined
1 1
High-Z High-Z
Low Defined
Defined/
Low
10
Low
Defined
14
Low High
High-Z High-Z
High High
High-Z Defined
PCH Pin States
S0/S1 S3
Defined Off
High Low
High Defined
High Low
High High
High High
High Low
Running
Defined Defined
1 1
High-Z High-Z
Defined Defined
Defined Off
Defined Off
High Defined
High-Z High-Z
High Off
Defined Defined
Datasheet
S4/S5
Off
Low
Defined
Low
Defined
2
Defined
Low
Defined
1
Low
Defined
Off
Off
Defined
High-Z
Off
Defined