Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 15

14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .......... 556
14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h .......... 556
14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ........................................ 556
14.1.8 BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2) ................................................................ 556
14.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F2).................................................................................... 557
14.1.10HTYPE—Header Type
(SATA–D31:F2).................................................................................... 557
14.1.11PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2) ....................................................................... 557
14.1.12PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2).................................................................................... 558
14.1.13SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F2) ........................................................................ 558
14.1.14SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F2) ........................................................................ 558
14.1.15BAR—Legacy Bus Master Base Address Register
(SATA–D31:F2).................................................................................... 559
14.1.16ABAR/SIDPBA1—AHCI Base Address Register/Serial ATA
Index Data Pair Base Address (SATA–D31:F2).......................................... 559
14.1.16.1When SCC is not 01h............................................................... 559
14.1.16.2When SCC is 01h .................................................................... 560
14.1.17SVID—Subsystem Vendor Identification Register
(SATA–D31:F2).................................................................................... 560
14.1.18SID—Subsystem Identification Register (SATA–D31:F2) ............................ 560
14.1.19CAP—Capabilities Pointer Register (SATA–D31:F2).................................... 560
14.1.20INT_LN—Interrupt Line Register (SATA–D31:F2) ...................................... 561
14.1.21INT_PN—Interrupt Pin Register (SATA–D31:F2)........................................ 561
14.1.22IDE_TIM — IDE Timing Register (SATA–D31:F2) ...................................... 561
14.1.23PID—PCI Power Management Capability Identification
Register (SATA–D31:F2) ....................................................................... 561
14.1.24PC—PCI Power Management Capabilities Register
(SATA–D31:F2).................................................................................... 562
14.1.25PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2) ....................................................................... 563
14.1.26MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) 564
14.1.27MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2) ........ 564
14.1.28MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2)....... 566
14.1.29MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2)............ 566
14.1.30MAP—Address Map Register (SATA–D31:F2) ............................................ 567
14.1.31PCS—Port Control and Status Register (SATA–D31:F2).............................. 568
14.1.32SCLKCG—SATA Clock Gating Control Register .......................................... 570
14.1.33SCLKGC—SATA Clock General Configuration Register ................................ 571
14.1.34SATACR0—SATA Capability Register 0 (SATA–D31:F2) .............................. 572
14.1.35SATACR1—SATA Capability Register 1 (SATA–D31:F2) .............................. 572
14.1.36FLRCID—FLR Capability ID (SATA–D31:F2) .............................................. 573
14.1.37FLRCLV—FLR Capability Length and Version (SATA–D31:F2) ...................... 573
14.1.38FLRC—FLR Control (SATA–D31:F2) ......................................................... 574
14.1.39ATC—APM Trapping Control Register (SATA–D31:F2) ................................ 574
14.1.40ATS—APM Trapping Status Register (SATA–D31:F2) ................................. 575
14.1.41SP Scratch Pad Register (SATA–D31:F2) ................................................. 575
14.1.42BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ........................... 576
14.1.43BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ........................ 578
14.1.44BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ........................ 578
14.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 579
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................... 580
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ............................... 581
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2) ................................................................................ 582
14.2.4 AIR—AHCI Index Register (D31:F2) ........................................................ 582
14.2.5 AIDR—AHCI Index Data Register (D31:F2) .............................................. 582
14.3 Serial ATA Index/Data Pair Superset Registers .................................................... 583
14.3.1 SINDX—Serial ATA Index (D31:F2)......................................................... 583
14.3.2 SDATA—Serial ATA Data (D31:F2).......................................................... 584
14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2) ............................ 584
14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2)............................ 585
Datasheet 15