Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 96

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 2 of 6)
Signal Name
FRAME#
GNT0#, GNT[3:1]#7/
GPIO[55, 53, 51]
IRDY#, TRDY#
PAR
PCIRST#
PERR#
PLOCK#
STOP#
LAD[3:0] / FWH[3:0]
LFRAME# / FWH[4]
7
INIT3_3V#
SATA[5:0]TXP,
SATA[5:0]TXN
SATALED#
SATAICOMPO
SCLOCK/GPIO22
SLOAD/GPIO38
SDATAOUT[1:0]/
GPIO[48,39]
SATA3RBIAS
SATA3ICOMPO
SATA3RCOMPO
PIRQ[A:D]#
PIRQ[H:E]# /
GPIO[5:2]
SERIRQ
USB[13:0][P,N]
USBRBIAS
96
Power During
1
Plane Reset
Core High-Z
Core High
Core High-Z
Core Low
Suspend Low
Core High-Z
Core High-Z
Core High-Z
LPC/FWH Interface
Core High
Core High
Core High
SATA Interface
Core High-Z
Core High-Z
Core High
Core High-Z (Input)
Core High-Z (Input)
Core High-Z
Terminated to
Core
Vss
Core High-Z
Core High-Z
Interrupts
Core High-Z
Core High-Z (Input)
Core High-Z
USB Interface
Suspend Low
Suspend High-Z
Immediately
S0/S1
1
after Reset
High-Z High-Z
High High
High-Z High-Z
Low Low
High High
High-Z High-Z
High-Z High-Z
High-Z High-Z
High High
High High
High High
High-Z Defined
High-Z Defined
High Defined
High-Z (Input) Defined
High-Z (Input) Defined
High-Z High-Z
Terminated to
Terminated
Vss to Vss
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z (Input) Defined
High-Z High-Z
Low Defined
High-Z High
PCH Pin States
S3 S4/S5
Off Off
Off Off
Off Off
Off Off
Low Low
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Defined Defined
High High
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