Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 507

LPC Interface Bridge Registers (D31:F0)
13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
Offset Address: A0h
Default Value:
Lockable:
Bit
15:11
10
9
8:5
4
3 (Mobile
Only)
3 (Desktop
Only)
2 (Mobile
Only)
2 (Desktop
Only)
1:0
Datasheet
0000h
No
Reserved
BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated
with the PCI Express* ports.
0 = The various PCI Express ports and processor cannot cause the PCI_EXP_STS
bit to go active.
1 = The various PCI Express ports and processor can cause the PCI_EXP_STS bit to
go active.
PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
Reserved
SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE
+ 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to
SMI_LOCK bit will have no effect (that is, once set, this bit can only be cleared by
PLTRST#).
Reserved
Pseudo CLKRUN_EN(PSEUDO_CLKRUN_EN) — R/W.
0 = Disable.
1 = Enable internal CLKRUN# logic to allow DMI PLL shutdown. This bit has no
impact on state of external CLKRUN# pin.
NOTES:
1. PSEUDO_CLKRUN_EN bit does not result in STP_PCI# assertion to actually
stop the external PCICLK.
2. This bit should be set mutually exclusive with the CLKRUN_EN bit. Setting
PSEUDO_CLKRUN_EN in a mobile SKU could result in unspecified behavior.
PCI CLKRUN# Enable (CLKRUN_EN) — R/W.
0 = Disable. PCH drives the CLKRUN# signal low.
1 = Enable CLKRUN# logic to control the system PCI clock using the CLKRUN# and
STP_PCI# signals.
NOTES:
1. When the SLP_EN# bit is set, the PCH drives the CLKRUN# signal low
regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and
LPC clocks continue running during a transition to a sleep state.
2. This bit should be set mutually exclusive with the PSEUDO_CLKRUN_EN bit.
Setting CLKRUN_EN in a non-mobile SKU could result in unspecified
behavior.
Reserved
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control
the rate at which periodic SMI# is generated.
00 = 64 seconds
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
Attribute: R/W, RO, R/WO
Size: 16-bit
Usage: ACPI, Legacy
Power Well: Core
Description
507