Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 783

PCI Express* Configuration Registers
19.1.38 LCTL2—Link Control 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 70h
Default Value:
Bit
15:4
3:0
19.1.39 MID—Message Signaled Interrupt Identifiers Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 80h–81h
Default Value:
Bit
15:8
7:0
19.1.40 MC—Message Signaled Interrupt Message Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 82–83h
Default Value:
Bit
15:8
7
6:4
3:1
0
Datasheet
71h
–
0001h
Reserved
Target Link Speed (TLS)— R/W. This field sets an upper limit on Link operational
speed by restricting the values advertised by the upstream component in its training
sequences.
0001b = 2.5 GT/s Target Link Speed
0010b = 5.0 GT/s and 2.5 GT/s Target Link Speeds
All other values reserved.
9005h
Next Pointer (NEXT) — RO. Indicates the location of the next pointer in the list.
Capability ID (CID) — RO. Capabilities ID indicates MSI.
0000h
Reserved
64 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only.
Multiple Message Enable (MME) — R/W. These bits are R/W for software
compatibility, but only one message is ever sent by the root port.
Multiple Message Capable (MMC) — RO. Only one message is required.
MSI Enable (MSIE) — R/W.
0 = MSI is disabled.
1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts.
NOTE: CMD.BME (D28:F0/F1/F2/F3/F4/F5/F6/F7:04h:bit 2) must be set for an MSI to
be generated. If CMD.BME is cleared, and this bit is set, no interrupts (not even
pin based) are generated.
Attribute: RO
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
Attribute: R/W, RO
Size: 16 bits
Description
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