Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 469

LPC Interface Bridge Registers (D31:F0)
13.1.32 BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)
Offset Address: DCh
Default Value:
Lockable:
Bit
7:6
5
4
3:2
1
0
Datasheet
20h
No
Reserved
SMM BIOS Write Protect Disable (SMM_BWP)— R/WLO.
This bit set defines when the BIOS region can be written by the host.
0 = BIOS region SMM protection is disabled. The BIOS Region is writable regardless if
processors are in SMM or not. (Set this field to 0 for legacy behavior)
1 = BIOS region SMM protection is enabled. The BIOS Region is not writable unless all
processors are in SMM.
Top Swap Status (TSS) — RO. This bit provides a read-only path to view the state of
the Top Swap bit that is at offset 3414h, bit 0.
SPI Read Configuration (SRC) — R/W. This 2-bit field controls two policies related to
BIOS reads on the SPI interface:
Bit 3 – Prefetch Enable
Bit 2 – Cache Disable
Settings are summarized below:
Bits 3:2 Description
No prefetching, but caching enabled. 64B demand reads load
00b the read buffer cache with "valid" data, allowing repeated code
fetches to the same line to complete quickly
No prefetching and no caching. One-to-one correspondence of
01b host BIOS reads to SPI cycles. This value can be used to invalidate
the cache.
Prefetching and Caching enabled. This mode is used for long
10b
sequences of short reads to consecutive addresses (i.e., shadowing).
Reserved. This is an invalid configuration, caching must be
11b
enabled when prefetching is enabled.
BIOS Lock Enable (BLE) — R/WLO.
0 = Setting the BIOSWE will not cause SMIs.
1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be
cleared by a PLTRST#
BIOS Write Enable (BIOSWE) — R/W.
0 = Only read cycles result in Firmware Hub I/F cycles.
1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is
written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is
generated. This ensures that only SMI code can update BIOS.
Attribute: R/WLO, R/W, RO
Size: 8 bit
Power Well: Core
Description
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