Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 356

Table 9-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)
Memory Range
FFE0 000h–FFE7 FFFFh
FFA0 0000h–FFA7 FFFFh
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
FFF0 0000h–FFF7 FFFFh
FFB0 0000h–FFB7 FFFFh
FFF8 0000h–FFFF FFFFh
FFB8 0000h–FFBF FFFFh
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
128 KB anywhere in 4-GB
1 KB anywhere in 4-GB
1 KB anywhere in 4-GB
16 KB anywhere in 64-bit
addressing space
FED0 X000h–FED0 X3FFh
NOTES:
1. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High
Precision Event Timers. If attempted, the lock is not honored, which means potential
deadlock conditions may occur.
2. PCI is the target when the Boot BIOS Destination selection bits are set to 10b (Chipset
Config Registers:Offset 3401 bits 11:10). When PCI selected, the Firmware Hub Decode
Enable bits have no effect.
356
Target
Firmware Hub (or
Firmware Hub (or
Firmware Hub (or
Firmware Hub (or
Firmware Hub (or
Firmware Hub (or
Firmware Hub (or
Firmware Hub (or
Integrated LAN
range Controller
USB EHCI
range Controller #1
USB EHCI
range Controller #2
Intel
Definition Audio
Host Controller
High Precision
Event Timers
All other
Dependency/Comments
Bit 12 in Firmware Hub Decode Enable register
2
PCI) is set
Bit 13 in Firmware Hub Decode Enable register
3
PCI) is set
Bit 14 in Firmware Hub Decode Enable register
2
PCI) is set
Always enabled.
The top two, 64 KB blocks of this range can be
2
PCI)
swapped, as described in
Bit 3 in Firmware Hub Decode Enable register
2
PCI) is set
Bit 2 in Firmware Hub Decode Enable register
2
PCI) is set
Bit 1 in Firmware Hub Decode Enable register
2
PCI) is set
Bit 0 in Firmware Hub Decode Enable register
2
PCI) is set
Enable using BAR in Device 25:Function 0
(Integrated LAN Controller)
Enable using standard PCI mechanism (Device
1
29, Function 0/7)
Enable using standard PCI mechanism (Device
1
26, Function 0/7)
®
High
Enable using standard PCI mechanism (Device
27, Function 0)
BIOS determines the "fixed" location which is
one of four, 1-KB ranges where X (in the first
1
column) is 0h, 1h, 2h, or 3h.
PCI None
Register and Memory Mapping
Section 7.4.1.
Datasheet