Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 487

LPC Interface Bridge Registers (D31:F0)
13.4.3 ICW2—Initialization Command Word 2 Register
Offset Address: Master Controller
Default Value:
ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[7:3] is used by the
processor to define the base address in the interrupt vector table for the interrupt
routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h
for the master controller and 70h for the slave controller.
Bit
Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the
7:3 interrupt vector table for the interrupt routines associated with each interrupt request
level input.
Interrupt Request Level — WO. When writing ICW2, these bits should all be 0.
During an interrupt acknowledge cycle, these bits are programmed by the interrupt
controller with the interrupt to be serviced. This is combined with bits [7:3] to form the
interrupt vector driven onto the data bus during the second INTA# cycle. The code is a
three bit binary code:
2:0
13.4.4 ICW3—Master Controller Initialization Command
Word 3 Register
Offset Address: 21h
Default Value:
Bit
7:3 0 = These bits must be programmed to 0.
Cascaded Interrupt Controller IRQ Connection — WO. This bit indicates that the
slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through
the slave controller's priority resolver. The slave controller's INTR output onto IRQ2.
2 IRQ2 then goes through the master controller's priority solver. If it wins, the INTR
signal is asserted to the processor, and the returning interrupt acknowledge returns the
interrupt vector for the slave controller.
1 = This bit must always be programmed to a 1.
1:0 0 = These bits must be programmed to 0.
Datasheet
Slave Controller
All bits undefined
Code Master Interrupt
000b IRQ0
001b IRQ1
010b IRQ2
011b IRQ3
100b IRQ4
101b IRQ5
110b IRQ6
111b IRQ7
All bits undefined
21h Attribute:
–
A1h Size:
–
Description
Slave Interrupt
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
Attribute:
Size:
Description
WO
8 bit /controller
WO
8 bits
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