Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 719

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Integrated Intel High Definition Audio Controller Registers
17.1.2.20 CORBCTL—CORB Control Register
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(Intel
Memory Address:HDBAR + 4Ch
Default Value:
Bit
7:2 Reserved.
Enable CORB DMA Engine — R/W.
0 = DMA stop
1 = DMA run
1
After software writes a 0 to this bit, the hardware may not stop immediately. The
hardware will physically update the bit to 0 when the DMA engine is truly stopped.
Software must read a 0 from this bit to verify that the DMA engine is truly stopped.
CORB Memory Error Interrupt Enable — R/W.
0
If this bit is set, the controller will generate an interrupt if the CMEI status bit (HDBAR
+ 4Dh: bit 0) is set.
17.1.2.21 CORBST—CORB Status Register
®
(Intel
Memory Address:HDBAR + 4Dh
Default Value:
Bit
7:1 Reserved.
CORB Memory Error Indication (CMEI) — R/WC.
1 = Controller detected an error in the path way between the controller and memory.
0
Software can clear this bit by writing a 1 to it. However, this type of error leaves the
audio subsystem in an un-viable state and typically requires a controller reset by
writing a 0 to the Controller Reset # bit (HDBAR + 08h: bit 0).
17.1.2.22 CORBSIZE—CORB Size Register
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Intel High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 4Eh
Default Value:
Bit
CORB Size Capability — RO. Hardwired to 0100b indicating that the PCH only
7:4
supports a CORB size of 256 CORB entries (1024B)
3:2 Reserved.
1:0 CORB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B)
Datasheet
High Definition Audio Controller—D27:F0)
00h
High Definition Audio Controller—D27:F0)
00h
This may be an ECC bit error or any other type of detectable data error which
renders the command data fetched invalid.
42h
Attribute: R/W
Size: 8 bits
Description
Attribute: R/WC
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
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