Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 513

LPC Interface Bridge Registers (D31:F0)
13.8.1.6 BM_BREAK_EN Register #2(PM—D31:F0)
Offset Address: AAh
Default Value:
Lockable:
Power Well:
Bit
7:1 Reserved
SATA3 Break Enable (SATA3_BREAK_EN) — R/W.
0
0 = SATA3 traffic will not cause BM_STS to be set.
1 = SATA3 traffic will cause BM_STS to be set.
13.8.1.7 BM_BREAK_EN Register (PM—D31:F0)
Offset Address: ABh
Default Value:
Lockable:
Power Well:
Bit
Storage Break Enable (STORAGE_BREAK_EN) — R/W.
7
0 = Serial ATA traffic will not cause BM_STS to be set.
1 = Serial ATA traffic will cause BM_STS to be set.
PCIE_BREAK_EN — R/W.
6
0 = PCI Express* traffic will not cause BM_STS to be set.
1 = PCI Express traffic will cause BM_STS to be set.
PCI_BREAK_EN — R/W.
5
0 = PCI traffic will not cause BM_STS to be set.
1 = PCI traffic will cause BM_STS to be set.
4:3 Reserved
EHCI_BREAK_EN — R/W.
2
0 = EHCI traffic will not cause BM_STS to be set.
1 = EHCI traffic will cause BM_STS to be set.
1 Reserved
HDA_BREAK_EN — R/W.
0
0 = Intel
1 = Intel
Datasheet
00h
No
Core
00h
No
Core
®
High Definition Audio traffic will not cause BM_STS to be set.
®
High Definition Audio traffic will cause BM_STS to be set.
Attribute: R/W, RO
Size: 8-bit
Usage: ACPI, Legacy
Description
Attribute: R/W
Size: 8-bit
Usage: ACPI, Legacy
Description
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