Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 524

Bit
8
7
6
5:3
2
1
0
524
RI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can
independently cause an SMI# or SCI, so this bit does not need to do so (unlike the
other bits in this register). Software clears this bit by writing a 1 to it.
0 = Wake event Not caused by the PCH's SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by the PCH's SMBus
logic. This bit will be set by the WAKE/SMI# command type, even if the system is
already awake. The SMI handler should then clear this bit.
NOTES:
1. The SMBus controller will independently cause an SMI# so this bit does not
need to do so (unlike the other bits in this register).
2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the
system is in the S0 state. Therefore, to avoid an instant wake on subsequent
transitions to sleep states, software must clear this bit after each reception of
the Wake/SMI# command or just prior to entering the sleep state.
3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by
software before the SMB_WAK_STS bit is cleared.
TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = TOC logic or thermal sensor logic did Not cause SCI.
1 = Set by hardware when the TCO logic or thermal sensor logic causes an SCI.
Reserved
SWGPE_STS — R/WC.
The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.
HOT_PLUG_STS — R/WC.
0 = This bit is cleared by writing a 1 to this bit position.
1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the
HOT_PLUG_EN and SCI_EN bits are set.
Reserved.
LPC Interface Bridge Registers (D31:F0)
Description
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