Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 544

13.10.5 GP_SER_BLINK—GP Serial Blink
Offset Address: GPIOBASE +1Ch
Default Value:
Lockable:
Bit
31:0
13.10.6 GP_SB_CMDSTS—GP Serial Blink Command Status
Offset Address: GPIOBASE +20h
Default Value:
Lockable:
Bit
31:24
23:22
21:16
15:9
8
7:1
0
544
00000000h
No
GP_SER_BLINK[31:0] — R/W. The setting of this bit has no effect if the
corresponding GPIO is programmed as an input or if the corresponding GPIO has the
GPO_BLINK bit set.
When set to a 0, the corresponding GPIO will function normally.
When using serial blink, this bit should be set to a 1 while the corresponding
GP_IO_SEL bit is set to 1. Setting the GP_IO_SEL bit to 0 after the GP_SER_BLINK bit
ensures PCH will not drive a 1 on the pin as an output. When this corresponding bit is
set to a 1 and the pin is configured to output mode, the serial blink capability is
enabled. The PCH will serialize messages through an open-drain buffer configuration.
The value of the corresponding GP_LVL bit remains unchanged and does not impact
the serial blink capability in any way.
Writes to this register have no effect when the corresponding pin is configured in
native mode and the read value returned is undefined.
00080000h
No
Reserved
Data Length Select (DLS) — R/W. This field determines the number of bytes to
serialize on GPIO.
00 = Serialize bits 7:0 of GP_SB_DATA (1 byte)
01 = Serialize bits 15:0 of GP_SB_DATA (2 bytes)
10 = Undefined – Software must not write this value
11 = Serialize bits 31:0 of GP_SB_DATA (4 bytes)
Software should not modify the value in this register unless the Busy bit is clear. Writes
to this register have no effect when the corresponding pin is configured in native mode
and the read value returned is undefined.
Data Rate Select (DRS) — R/W. This field selects the number of 120ns time intervals
to count between Manchester data transitions. The default of 8h results in a 960 ns
minimum time between transitions. A value of 0h in this register produces undefined
behavior.
Software should not modify the value in this register unless the Busy bit is clear.
Reserved
Busy — RO. This read-only status bit is the hardware indication that a serialization is
in progress. Hardware sets this bit to 1 based on the Go bit being set. Hardware clears
this bit when the Go bit is cleared by the hardware.
Reserved
Go — R/W. This bit is set to 1 by software to start the serialization process. Hardware
clears the bit after the serialized data is sent. Writes of 0 to this register have no effect.
Software should not write this bit to 1 unless the Busy status bit is cleared.
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
Attribute: R/W, RO
Size: 32-bit
Power Well: Core
Description
Datasheet