Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 707

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Integrated Intel High Definition Audio Controller Registers
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Table 17-2. Intel High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel
HDBAR +
Offset
5Ah–5Bh
5Ch
5Dh
5Eh
60h–63h
64h–67h
68h–69h
70h–73h
74h–77h
80–82h
83h
84h–87h
88h–8Bh
8Ch–8Dh
8Eh–8F
90h–91h
92h–93h
98h–9Bh
9Ch–9Fh
A0h–A2h
A3h
A4h–A7h
A8h–ABh
ACh–ADh
AEh–AFh
B0h–B1h
B2h–B3h
B8h–BBh
BCh–BFh
C0h–C2h
C3h
Datasheet
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High Definition Audio D27:F0) (Sheet 2 of 4)
Mnemonic
RINTCNT Response Interrupt Count
RIRBCTL RIRB Control
RIRBSTS RIRB Status
RIRBSIZE RIRB Size
IC Immediate Command
IR Immediate Response
IRS Immediate Command Status
DPLBASE DMA Position Lower Base Address
DPUBASE DMA Position Upper Base Address
Input Stream Descriptor 0 (ISD0)
ISD0CTL
Control
ISD0STS ISD0 Status
ISD0LPIB ISD0 Link Position in Buffer
ISD0CBL ISD0 Cyclic Buffer Length
ISD0LVI ISD0 Last Valid Index
ISD0FIFOW ISD0 FIFO Watermark
ISD0FIFOS ISD0 FIFO Size
ISD0FMT ISD0 Format
ISD0 Buffer Descriptor List Pointer –
ISD0BDPL
Lower Base Address
ISD0 Buffer Description List Pointer –
ISD0BDPU
Upper Base Address
Input Stream Descriptor 1(ISD01)
ISD1CTL
Control
ISD1STS ISD1 Status
ISD1LPIB ISD1 Link Position in Buffer
ISD1CBL ISD1 Cyclic Buffer Length
ISD1LVI ISD1 Last Valid Index
ISD1FIFOW ISD1 FIFO Watermark
ISD1FIFOS ISD1 FIFO Size
ISD1FMT ISD1 Format
ISD1 Buffer Descriptor List Pointer –
ISD1BDPL
Lower Base Address
ISD1 Buffer Description List Pointer –
ISD1BDPU
Upper Base Address
Input Stream Descriptor 2 (ISD2)
ISD2CTL
Control
ISD2STS ISD2 Status
Register Name Default Access
0000h R/W
00h R/W
00h R/WC
42h RO
00000000h R/W
00000000h RO
R/W, R/
0000h
WC
00000000h R/W, RO
00000000h R/W
040000h R/W, RO
00h R/WC, RO
00000000h RO
00000000h R/W
0000h R/W
0004h R/W
0000h R/W
0000h R/W
00000000h R/W, RO
00000000h R/W
040000h R/W, RO
00h R/WC, RO
00000000h RO
00000000h R/W
0000h R/W
0004h R/W
0000h R/W
0000h R/W
00000000h R/W, RO
00000000h R/W
040000h R/W, RO
00h R/WC, RO
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