Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 813

Serial Peripheral Interface (SPI)
21.1.3 HSFC—Hardware Sequencing Flash Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 06hAttribute:
Default Value:
Note: This register is only applicable when SPI device is in descriptor mode.
Bit
Flash SPI SMI# Enable (FSMIE) — R/W. When set to 1, the SPI asserts an SMI#
15
request whenever the Flash Cycle Done bit is 1.
14 Reserved
Flash Data Byte Count (FDBC) — R/W. This field specifies the number of bytes to
shift in or out during the data portion of the SPI cycle. The contents of this register are
0s based with 0b representing 1 byte and 111111b representing 64 bytes. The number
13:8
of bytes transferred is the value of this field plus 1.
This field is ignored for the Block Erase command.
7:3 Reserved
FLASH Cycle (FCYCLE) — R/W. This field defines the Flash SPI cycle type generated
to the FLASH when the FGO bit is set as defined below:
00 = Read (1 up to 64 bytes by setting FDBC)
2:1
01 = Reserved
10 = Write (1 up to 64 bytes by setting FDBC)
11 = Block Erase
Flash Cycle Go (FGO) — R/W/S. A write to this register with a 1 in this bit initiates a
request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware
when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the
cycle is complete, the FDONE bit is set.
Software is forbidden to write to any register in the HSFLCTL register between the FGO
0
bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be
ignored by hardware.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
This bit always returns 0 on reads.
21.1.4 FADDR—Flash Address Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 08hAttribute:
Default Value:
Bit
31:25 Reserved
Flash Linear Address (FLA) — R/W. The FLA is the starting byte linear address of a
SPI Read or Write cycle or an address within a Block for the Block Erase command. The
Flash Linear Address must fall within a region for which BIOS has access permissions.
24:0
Hardware must convert the FLA into a Flash Physical Address (FPA) before running this
cycle on the SPI bus.
Datasheet
0000hSize:
00000000h
R/W, R/WS
16 bits
Description
R/W
Size: 32 bits
Description
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